Pub Date : 1994-10-16DOI: 10.1109/GAAS.1994.636941
R. Anholt, J. Pence, E. Godshalk
The accuracy of W-band on-wafer S-parameter measurements and direct equivalent-circuit parameter extraction (ECP) techniques for characterizing InP lattice-matched and pHEMTs to 110 GHz is examined. The effects of transverse propagation delays on high-frequency equivalent circuits are discussed. Measurements show that as long as pad capacitances are carefully determined, frequency-independent cold- and hot-FET ECPs can be direct-extracted across the entire frequency band from 1 to 110 GHz, and the derived models can be used to reliably design amplifiers to 110 GHz.
{"title":"On-wafer HEMT characterization to 110 GHz","authors":"R. Anholt, J. Pence, E. Godshalk","doi":"10.1109/GAAS.1994.636941","DOIUrl":"https://doi.org/10.1109/GAAS.1994.636941","url":null,"abstract":"The accuracy of W-band on-wafer S-parameter measurements and direct equivalent-circuit parameter extraction (ECP) techniques for characterizing InP lattice-matched and pHEMTs to 110 GHz is examined. The effects of transverse propagation delays on high-frequency equivalent circuits are discussed. Measurements show that as long as pad capacitances are carefully determined, frequency-independent cold- and hot-FET ECPs can be direct-extracted across the entire frequency band from 1 to 110 GHz, and the derived models can be used to reliably design amplifiers to 110 GHz.","PeriodicalId":328819,"journal":{"name":"Proceedings of 1994 IEEE GaAs IC Symposium","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117205889","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-10-16DOI: 10.1109/GAAS.1994.636951
F. Bonani, G. Ghione, M. Pirola, C. Naldi
A three-dimensional large-scale thermal simulation tool is applied to the design of power III-V devices and integrated circuits (ICs). After a short description of the modelling approach, which allows for non-linear multilayered and thinned substrates, via holes, and heat conduction through surface metallizations, simulation examples are discussed concerning GEC-Marconi power MESFETs with improved heat sinking and power ICs.
{"title":"Large-scale, computer-aided thermal design of power GaAs integrated devices and circuits","authors":"F. Bonani, G. Ghione, M. Pirola, C. Naldi","doi":"10.1109/GAAS.1994.636951","DOIUrl":"https://doi.org/10.1109/GAAS.1994.636951","url":null,"abstract":"A three-dimensional large-scale thermal simulation tool is applied to the design of power III-V devices and integrated circuits (ICs). After a short description of the modelling approach, which allows for non-linear multilayered and thinned substrates, via holes, and heat conduction through surface metallizations, simulation examples are discussed concerning GEC-Marconi power MESFETs with improved heat sinking and power ICs.","PeriodicalId":328819,"journal":{"name":"Proceedings of 1994 IEEE GaAs IC Symposium","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127153930","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-10-16DOI: 10.1109/GAAS.1994.636914
S. Marsh, R. G. Arnold
This paper describes the first monolithic microwave integrated circuit bandstop filter using an inverted gyrator design. Operating up to 3 GHz it also represents the highest reported frequency application of a gyrator filter design. New active bias configurations were developed to achieve a stable gyrator response and assessment of the filters' tuning speed and control voltage requirements has shown its suitability for digital control in applications requiring frequency agility. The individual MMICs are capable of tuning a 3%, -30 dB attenuation bandwidth, over greater than an octave, and a series combination of two MMICs have a tuneable stopband from 0.7 to 3.3 GHz.
{"title":"MMIC gyrator bandstop filter with ultra-wideband tuning","authors":"S. Marsh, R. G. Arnold","doi":"10.1109/GAAS.1994.636914","DOIUrl":"https://doi.org/10.1109/GAAS.1994.636914","url":null,"abstract":"This paper describes the first monolithic microwave integrated circuit bandstop filter using an inverted gyrator design. Operating up to 3 GHz it also represents the highest reported frequency application of a gyrator filter design. New active bias configurations were developed to achieve a stable gyrator response and assessment of the filters' tuning speed and control voltage requirements has shown its suitability for digital control in applications requiring frequency agility. The individual MMICs are capable of tuning a 3%, -30 dB attenuation bandwidth, over greater than an octave, and a series combination of two MMICs have a tuneable stopband from 0.7 to 3.3 GHz.","PeriodicalId":328819,"journal":{"name":"Proceedings of 1994 IEEE GaAs IC Symposium","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122142347","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-10-16DOI: 10.1109/GAAS.1994.636918
J. Hallmark, C. Shurboff, B. Ooms, R. Lucero, J. Abrokwah, Jenn‐Hwa Huang
4 K SRAM and 16 bit multiply/accumulate DSP blocks have been designed and fabricated in Complementary heterostructure GaAs. Both circuits operate from 1.5 V to below 0.9 V. The SRAM uses 28,272 transistors in an area of 2.44 mm/sup 2/. Cell size is 278 /spl mu/m/sup 2/ at 1.0 /spl mu/m gate length. Measured results show an access delay of 5.3 ns at 1.5 V and 15.0 ns at 0.9 V. At 0.9 V, total power is 0.36 mW. The CGaAs multiplier uses a 16-bit modified Booth architecture with a 3-way 40-bit accumulator. The multiplier uses 11,200 transistors in an area of 1.23 mm/sup 2/. Measured delay is 19.0 ns at 1.5 V and 44.7 ns at 0.9 V. At 0.9 V, total current is less than 0.4 mA.
{"title":"0.9 V DSP blocks: a 15 ns 4 K SRAM and a 45 ns 16-bit multiply/accumulator","authors":"J. Hallmark, C. Shurboff, B. Ooms, R. Lucero, J. Abrokwah, Jenn‐Hwa Huang","doi":"10.1109/GAAS.1994.636918","DOIUrl":"https://doi.org/10.1109/GAAS.1994.636918","url":null,"abstract":"4 K SRAM and 16 bit multiply/accumulate DSP blocks have been designed and fabricated in Complementary heterostructure GaAs. Both circuits operate from 1.5 V to below 0.9 V. The SRAM uses 28,272 transistors in an area of 2.44 mm/sup 2/. Cell size is 278 /spl mu/m/sup 2/ at 1.0 /spl mu/m gate length. Measured results show an access delay of 5.3 ns at 1.5 V and 15.0 ns at 0.9 V. At 0.9 V, total power is 0.36 mW. The CGaAs multiplier uses a 16-bit modified Booth architecture with a 3-way 40-bit accumulator. The multiplier uses 11,200 transistors in an area of 1.23 mm/sup 2/. Measured delay is 19.0 ns at 1.5 V and 44.7 ns at 0.9 V. At 0.9 V, total current is less than 0.4 mA.","PeriodicalId":328819,"journal":{"name":"Proceedings of 1994 IEEE GaAs IC Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128209933","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-10-16DOI: 10.1109/GAAS.1994.636970
R. Walden
Analog-to-digital converters are ubiquitous, critical components of signal processing systems. This presentation surveys the state-of-the-art for ADCs and includes both experimental converters and commercially available parts. The shape of the distribution on a resolution vs. sampling rate graph provides insight into ADC performance limitations. For sampling frequencies ranging from /spl sim/0.5 MSPS to /spl sim/4 GSPS, resolution falls off by /spl sim/1 bit for every doubling of the sampling rate. This effect can be related to aperture jitter. For ADCs operating at /spl ges/4 GSPS, the speed of the device technology is a limiting factor. In order to push back these limits, many ADC architectures have been proposed and implemented.
{"title":"Analog-to-digital converter technology comparison","authors":"R. Walden","doi":"10.1109/GAAS.1994.636970","DOIUrl":"https://doi.org/10.1109/GAAS.1994.636970","url":null,"abstract":"Analog-to-digital converters are ubiquitous, critical components of signal processing systems. This presentation surveys the state-of-the-art for ADCs and includes both experimental converters and commercially available parts. The shape of the distribution on a resolution vs. sampling rate graph provides insight into ADC performance limitations. For sampling frequencies ranging from /spl sim/0.5 MSPS to /spl sim/4 GSPS, resolution falls off by /spl sim/1 bit for every doubling of the sampling rate. This effect can be related to aperture jitter. For ADCs operating at /spl ges/4 GSPS, the speed of the device technology is a limiting factor. In order to push back these limits, many ADC architectures have been proposed and implemented.","PeriodicalId":328819,"journal":{"name":"Proceedings of 1994 IEEE GaAs IC Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128415845","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-10-16DOI: 10.1109/GAAS.1994.636988
Y. Kuriyama, J. Akagi, T. Sugiyama, S. Hongo, K. Tsuda, N. Iizuka, Masao Obara
In this paper, we report two types of broad-band amplifiers implemented with AlGaAs/GaAs HBT's. One is a Darlington feedback amplifier and the other is a transimpedance amplifier. In the former circuit, a DC gain of 9.5 dB and a -3 dB bandwidth of 40 GHz were achieved. In the latter circuit, a transimpedance gain of 50 dB/spl Omega/ and a -3 dB bandwidth of 27 GHz were achieved. To our best knowledge, they are the highest speed in each circuit configuration.
{"title":"DC to 40 GHz broad-band amplifiers using AlGaAs/GaAs HBT's","authors":"Y. Kuriyama, J. Akagi, T. Sugiyama, S. Hongo, K. Tsuda, N. Iizuka, Masao Obara","doi":"10.1109/GAAS.1994.636988","DOIUrl":"https://doi.org/10.1109/GAAS.1994.636988","url":null,"abstract":"In this paper, we report two types of broad-band amplifiers implemented with AlGaAs/GaAs HBT's. One is a Darlington feedback amplifier and the other is a transimpedance amplifier. In the former circuit, a DC gain of 9.5 dB and a -3 dB bandwidth of 40 GHz were achieved. In the latter circuit, a transimpedance gain of 50 dB/spl Omega/ and a -3 dB bandwidth of 27 GHz were achieved. To our best knowledge, they are the highest speed in each circuit configuration.","PeriodicalId":328819,"journal":{"name":"Proceedings of 1994 IEEE GaAs IC Symposium","volume":"287 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123444997","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-10-16DOI: 10.1109/GAAS.1994.636990
S. Chu, U. Wohlert, G. Jackson, M. Adlerstein, J. B. Cole, M. Zaitlin
A Ka-band HBT two-stage LNA has been developed. This circuit is to be used in a multifunction T/R module which includes both analog and digital functions. The measured noise figure is 5 dB from 30 GHz to 34 GHz, with an associated gain of better than 7.5 dB. A single-stage LNA has also been developed. The measured noise figure is 4 dB from 33 GHz to 35 GHz with an associated gain of 4 dB. These results are the best yet reported at Ka-band for a HBT LNA. The amplifiers have been designed to minimize the noise measure.
{"title":"A Ka-band HBT two-stage LNA","authors":"S. Chu, U. Wohlert, G. Jackson, M. Adlerstein, J. B. Cole, M. Zaitlin","doi":"10.1109/GAAS.1994.636990","DOIUrl":"https://doi.org/10.1109/GAAS.1994.636990","url":null,"abstract":"A Ka-band HBT two-stage LNA has been developed. This circuit is to be used in a multifunction T/R module which includes both analog and digital functions. The measured noise figure is 5 dB from 30 GHz to 34 GHz, with an associated gain of better than 7.5 dB. A single-stage LNA has also been developed. The measured noise figure is 4 dB from 33 GHz to 35 GHz with an associated gain of 4 dB. These results are the best yet reported at Ka-band for a HBT LNA. The amplifiers have been designed to minimize the noise measure.","PeriodicalId":328819,"journal":{"name":"Proceedings of 1994 IEEE GaAs IC Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121475005","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-10-16DOI: 10.1109/GAAS.1994.636995
Q.C. Streit, D. Umemoto, K. Kobayashi, A. Oki
We have successfully achieved monolithic integration of HEMT and HBT devices in the same microwave circuit for the first time. We have used selective molecular beam epitaxy and a newly developed merged-processing technology to produce novel microwave integrated circuits that incorporate both pseudomorphic InGaAs-GaAs HEMTs and GaAs-AlGaAs HBTs on the same chip. The HEMT devices use 0.2 /spl mu/m gates, while the HBT devices use 2 and 3 /spl mu/m emitters. The performance of the merged HEMT and HBT devices is equivalent to that of baseline devices fabricated by our normal single-technology process. The HEMT devices achieve g/sub m/=600 mS/mm, while 3/spl times/10 /spl mu/m/sup 2/ HBTs achieve /spl beta//spl sim/50 at I/sub c/=1 mA. A monolithic HEMT-HBT integrated circuit is presented that uses active HBT regulation of a HEMT low-noise amplifier. The noise and gain performance of the monolithic HBT regulated 5-10 GHz HEMT LNA is shown to be equivalent to that of the same amplifier fabricated using our baseline HEMT-only process.
{"title":"Monolithic HEMT-HBT integration for novel microwave circuit applications","authors":"Q.C. Streit, D. Umemoto, K. Kobayashi, A. Oki","doi":"10.1109/GAAS.1994.636995","DOIUrl":"https://doi.org/10.1109/GAAS.1994.636995","url":null,"abstract":"We have successfully achieved monolithic integration of HEMT and HBT devices in the same microwave circuit for the first time. We have used selective molecular beam epitaxy and a newly developed merged-processing technology to produce novel microwave integrated circuits that incorporate both pseudomorphic InGaAs-GaAs HEMTs and GaAs-AlGaAs HBTs on the same chip. The HEMT devices use 0.2 /spl mu/m gates, while the HBT devices use 2 and 3 /spl mu/m emitters. The performance of the merged HEMT and HBT devices is equivalent to that of baseline devices fabricated by our normal single-technology process. The HEMT devices achieve g/sub m/=600 mS/mm, while 3/spl times/10 /spl mu/m/sup 2/ HBTs achieve /spl beta//spl sim/50 at I/sub c/=1 mA. A monolithic HEMT-HBT integrated circuit is presented that uses active HBT regulation of a HEMT low-noise amplifier. The noise and gain performance of the monolithic HBT regulated 5-10 GHz HEMT LNA is shown to be equivalent to that of the same amplifier fabricated using our baseline HEMT-only process.","PeriodicalId":328819,"journal":{"name":"Proceedings of 1994 IEEE GaAs IC Symposium","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114772846","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-10-16DOI: 10.1109/GAAS.1994.636945
S. Sugitani, Y. Yamane, T. Nittono, H. Yamazaki, K. Nishimura, K. Yamasaki
This paper describes a new pseudomorphic InGaP/InGaAs/GaAs heterostructure MESFET (HMESFET) technology combined with a refractory self-aligned gate process for ultra-high-speed analog-digital hybrid type ICs. InGaAs is used as the thin channel layer for its higher carrier concentration. An undoped InGaP thin layer is used to improve breakdown voltage. A planar device process has been successfully developed by using self-aligned n/sup +/-implantation technology with refractory gate metal and oxygen ion implantation for device isolation. Symmetric and asymmetric FETs can be produced with the same technology by only changing the implantation angle.
{"title":"Self-aligned InGaP/InGaAs/GaAs heterostructure MESFET technology for analog-digital hybrid type ICs","authors":"S. Sugitani, Y. Yamane, T. Nittono, H. Yamazaki, K. Nishimura, K. Yamasaki","doi":"10.1109/GAAS.1994.636945","DOIUrl":"https://doi.org/10.1109/GAAS.1994.636945","url":null,"abstract":"This paper describes a new pseudomorphic InGaP/InGaAs/GaAs heterostructure MESFET (HMESFET) technology combined with a refractory self-aligned gate process for ultra-high-speed analog-digital hybrid type ICs. InGaAs is used as the thin channel layer for its higher carrier concentration. An undoped InGaP thin layer is used to improve breakdown voltage. A planar device process has been successfully developed by using self-aligned n/sup +/-implantation technology with refractory gate metal and oxygen ion implantation for device isolation. Symmetric and asymmetric FETs can be produced with the same technology by only changing the implantation angle.","PeriodicalId":328819,"journal":{"name":"Proceedings of 1994 IEEE GaAs IC Symposium","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125600645","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-10-16DOI: 10.1109/GAAS.1994.636999
S. Yamahata, K. Kurishima, H. Nakajima, T. Kobayashi, Y. Matsuoka
The high-frequency performance of small scale InP/InGaAs DHBTs with InGaAsP in the collector that has a highly Zn-doped base was investigated using various emitter-widths and lengths as functions of collector current I/sub C/ and collector/emitter voltage V/sub CE/. Narrowing the emitter-width is significantly more effective for increasing f/sub max/ than shortening the emitter-lengths. A DHBT with a narrow 0.8-/spl mu/m emitter-metal has an ultra-high f/sub max/ of 267 GHz and f/sub T/ of 144 GHz at an I/sub C/ as low as 4 mA. This increase in f/sub max/ is attributed to the low product of the base resistance and reduced base/collector capacitance.
{"title":"Ultra-high f/sub max/ and f/sub T/ InP/InGaAs double-heterojunction bipolar transistors with step-graded InGaAsP collector","authors":"S. Yamahata, K. Kurishima, H. Nakajima, T. Kobayashi, Y. Matsuoka","doi":"10.1109/GAAS.1994.636999","DOIUrl":"https://doi.org/10.1109/GAAS.1994.636999","url":null,"abstract":"The high-frequency performance of small scale InP/InGaAs DHBTs with InGaAsP in the collector that has a highly Zn-doped base was investigated using various emitter-widths and lengths as functions of collector current I/sub C/ and collector/emitter voltage V/sub CE/. Narrowing the emitter-width is significantly more effective for increasing f/sub max/ than shortening the emitter-lengths. A DHBT with a narrow 0.8-/spl mu/m emitter-metal has an ultra-high f/sub max/ of 267 GHz and f/sub T/ of 144 GHz at an I/sub C/ as low as 4 mA. This increase in f/sub max/ is attributed to the low product of the base resistance and reduced base/collector capacitance.","PeriodicalId":328819,"journal":{"name":"Proceedings of 1994 IEEE GaAs IC Symposium","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128181166","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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