Ming-Der Shieh, Chien-Ming Wu, Hsiao-Hsing Chou, Min-Hui Chen, Chia-Liang Liu
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引用次数: 11
Abstract
This paper describes the design of de-interleaver and Viterbi decoder for the Eureka-147 DAB system and their corresponding VLSI implementations. We emphasize on how to efficiently handle four DAB transmission modes, time/frequency de-interleaving and path metric/survivor memory management in our development. Results show that our implementation has the potential of consuming less silicon area and power dissipation, and facilitating the extension for high transmission rate requirement.
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