Reliability of a CBGA miroproessor package incorpoating a decoupling capacitor array

Abstract

In this work, the reliability of a novel advanced packaging design for microprocessors has been explored. The new architecture consists of a Ceramic Ball Grid Array (CBGA) package with a flip chip die on a high CTE ceramic substrate, and an array of decoupling capacitors used within the second level interconnects. The capacitors are modified chip capacitors that are soldered immediately beneath the CBGA substrate in a square array that replaces some or all of the ball grid array solder joints. This location for the capacitors improves electrical performance of the microprocessor package (reduces noise/crosstalk and increases speed), and also provides resistance to solder joint collapse. The value of the designs in this investigation is in moving the decoupling capacitive elements of the package closer to the die while having a comparable mechanical reliability to an analogous BGA package. Test assemblies of the new packaging concept containing daisy chain test die have been prepared and subjected to thermal cycling reliability testing. Both lead free and Sn-Pb solder joint options have been examined. Weibull failure plots of the recorded failure data have been created, and failure analysis has been performed to identify failure locations and failure modes.