Channelized front-ends for broadband signal processing with relaxed anti-aliasing filtering

V. Singh, Wei-Gi Ho, R. Gharpurey
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引用次数: 2

Abstract

A digital post-processing approach for reducing the anti-aliasing requirement in a frequency-folding channelizer architecture is described. The channelizer decomposes a broadband spectrum into multiple sub-bands. A signal of bandwidth N/2fLO is downconverted into N paths that are clocked using rectangular, non-overlapping pulse waveforms at a fundamental frequency of fLO with a duty-cycle of 1/N. All portions of the input are aliased onto a baseband signal of bandwidth fLO/2, which is low-pass filtered and applied to N sub-ADCs with identical sampling clocks. Individual sub-bands are selected in the digital domain. Aliasing between sub-bands is also removed after digitization. This is used to reduce the order of the anti-aliasing filters in the analog signal paths, which can potentially reduce power and design complexity. It is shown that a filter-order of at least one is necessary in the analog-domain to apply digital post-processing. The approach is verified in simulation.
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用于宽带信号处理的信道化前端,具有宽松的抗混叠滤波
描述了一种数字后处理方法,用于降低频率折叠信道器结构中的抗混叠要求。信道器将宽带频谱分解成多个子频段。带宽为N/2fLO的信号被下转换成N条路径,这些路径使用矩形、无重叠的脉冲波形以fLO的基频进行时钟处理,占空比为1/N。输入的所有部分都混叠到带宽为fLO/2的基带信号上,该基带信号经过低通滤波并应用于具有相同采样时钟的N个子adc。在数字域中选择单个子带。数字化后,子带间的混叠也被消除。这用于降低模拟信号路径中抗混叠滤波器的阶数,从而潜在地降低功耗和设计复杂性。结果表明,要在模拟域中应用数字后处理,至少需要一个1阶的滤波器。仿真验证了该方法的有效性。
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