Pub Date : 2015-12-17DOI: 10.1109/DCAS.2015.7356586
M. Ahmadi, W. Namgoong
A low-power configurable design for an asynchronous SAR ADC that is suitable for analog front-end of sensor ASICs is presented. The proposed architecture employs a majority vote based comparator capable of providing programmable noise performance. The proposed asynchronous digital logic determines the majority vote by employing two counters at the comparator differential output. Simulation result shows that the total number of votes in a 12-bit ADC can be reduced by 42% using a split-counter majority voter. Further reduction is possible by allocating the number of votes non-uniformly with more votes closer to LSB cycles. Simulation results show that the total number of votes can be reduced by 65% in a 12-bit ADC with the non-uniform vote allocation. When compared to a non-voting conventional 12-bit SAR ADC with the same overall performance, the comparator power is reduced by 46%.
{"title":"Asynchronous SAR logic design using majority vote comparison for configurable SAR ADCs","authors":"M. Ahmadi, W. Namgoong","doi":"10.1109/DCAS.2015.7356586","DOIUrl":"https://doi.org/10.1109/DCAS.2015.7356586","url":null,"abstract":"A low-power configurable design for an asynchronous SAR ADC that is suitable for analog front-end of sensor ASICs is presented. The proposed architecture employs a majority vote based comparator capable of providing programmable noise performance. The proposed asynchronous digital logic determines the majority vote by employing two counters at the comparator differential output. Simulation result shows that the total number of votes in a 12-bit ADC can be reduced by 42% using a split-counter majority voter. Further reduction is possible by allocating the number of votes non-uniformly with more votes closer to LSB cycles. Simulation results show that the total number of votes can be reduced by 65% in a 12-bit ADC with the non-uniform vote allocation. When compared to a non-voting conventional 12-bit SAR ADC with the same overall performance, the comparator power is reduced by 46%.","PeriodicalId":162311,"journal":{"name":"2015 IEEE Dallas Circuits and Systems Conference (DCAS)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133543328","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-12-17DOI: 10.1109/DCAS.2015.7356596
V. Singh, Wei-Gi Ho, R. Gharpurey
A digital post-processing approach for reducing the anti-aliasing requirement in a frequency-folding channelizer architecture is described. The channelizer decomposes a broadband spectrum into multiple sub-bands. A signal of bandwidth N/2fLO is downconverted into N paths that are clocked using rectangular, non-overlapping pulse waveforms at a fundamental frequency of fLO with a duty-cycle of 1/N. All portions of the input are aliased onto a baseband signal of bandwidth fLO/2, which is low-pass filtered and applied to N sub-ADCs with identical sampling clocks. Individual sub-bands are selected in the digital domain. Aliasing between sub-bands is also removed after digitization. This is used to reduce the order of the anti-aliasing filters in the analog signal paths, which can potentially reduce power and design complexity. It is shown that a filter-order of at least one is necessary in the analog-domain to apply digital post-processing. The approach is verified in simulation.
{"title":"Channelized front-ends for broadband signal processing with relaxed anti-aliasing filtering","authors":"V. Singh, Wei-Gi Ho, R. Gharpurey","doi":"10.1109/DCAS.2015.7356596","DOIUrl":"https://doi.org/10.1109/DCAS.2015.7356596","url":null,"abstract":"A digital post-processing approach for reducing the anti-aliasing requirement in a frequency-folding channelizer architecture is described. The channelizer decomposes a broadband spectrum into multiple sub-bands. A signal of bandwidth N/2fLO is downconverted into N paths that are clocked using rectangular, non-overlapping pulse waveforms at a fundamental frequency of fLO with a duty-cycle of 1/N. All portions of the input are aliased onto a baseband signal of bandwidth fLO/2, which is low-pass filtered and applied to N sub-ADCs with identical sampling clocks. Individual sub-bands are selected in the digital domain. Aliasing between sub-bands is also removed after digitization. This is used to reduce the order of the anti-aliasing filters in the analog signal paths, which can potentially reduce power and design complexity. It is shown that a filter-order of at least one is necessary in the analog-domain to apply digital post-processing. The approach is verified in simulation.","PeriodicalId":162311,"journal":{"name":"2015 IEEE Dallas Circuits and Systems Conference (DCAS)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127961792","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-12-17DOI: 10.1109/DCAS.2015.7356583
Mikel Ash, R. Flake, T. R. Viswanathan
An exponential pulse generator for use in a Time-Domain Reflectometer is described. This pulse has the property that its leading edge does not suffer distortion while propagating in dispersive lossy transmission lines. It thus enables accurate measurement of time of flight of a single pulse reflected by an impedance-discontinuity in a faulty transmission line. The design of a precision pulse generator that enables the control of pulse-amplitude, pulse-rate and the time constant of its exponentially rising edge is described. A key feature of the design is a compensation scheme to eliminate the temperature variation arising from the reverse saturation current as well as the thermal voltage in the exponential v-i characteristics of a p-n junction used to generate the pulse. Here we present simulation results as well as a circuit using discrete components interconnected on a printed circuit board. Experimental results from a calibrated prototype show that a fault 100 meters away along a cable can be located with a precision of a fraction of a millimeter.
{"title":"Exponential pulse generator for a time domain reflectometer","authors":"Mikel Ash, R. Flake, T. R. Viswanathan","doi":"10.1109/DCAS.2015.7356583","DOIUrl":"https://doi.org/10.1109/DCAS.2015.7356583","url":null,"abstract":"An exponential pulse generator for use in a Time-Domain Reflectometer is described. This pulse has the property that its leading edge does not suffer distortion while propagating in dispersive lossy transmission lines. It thus enables accurate measurement of time of flight of a single pulse reflected by an impedance-discontinuity in a faulty transmission line. The design of a precision pulse generator that enables the control of pulse-amplitude, pulse-rate and the time constant of its exponentially rising edge is described. A key feature of the design is a compensation scheme to eliminate the temperature variation arising from the reverse saturation current as well as the thermal voltage in the exponential v-i characteristics of a p-n junction used to generate the pulse. Here we present simulation results as well as a circuit using discrete components interconnected on a printed circuit board. Experimental results from a calibrated prototype show that a fault 100 meters away along a cable can be located with a precision of a fraction of a millimeter.","PeriodicalId":162311,"journal":{"name":"2015 IEEE Dallas Circuits and Systems Conference (DCAS)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125394351","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-12-17DOI: 10.1109/DCAS.2015.7356605
Amean Al-Safi, B. Bazuin
Polyphase filter bank channalizers are essential components in numerous communication systems involving signal separation and sample rate conversion. In this paper, a novel fully parallelized 64 channels polyphase channalizer has been implemented using general purposes graphic processing units (GPGPU). The implemented models have been compared with a corresponding serial implemented model. The comparison indicates that the parallel models provide a computation speed of 9-16 times faster than the serial one using Nvidia GeForce GT520M and Quadro 600 GPUs.
{"title":"GPU based implementation of a 64-channel polyphase channalizer","authors":"Amean Al-Safi, B. Bazuin","doi":"10.1109/DCAS.2015.7356605","DOIUrl":"https://doi.org/10.1109/DCAS.2015.7356605","url":null,"abstract":"Polyphase filter bank channalizers are essential components in numerous communication systems involving signal separation and sample rate conversion. In this paper, a novel fully parallelized 64 channels polyphase channalizer has been implemented using general purposes graphic processing units (GPGPU). The implemented models have been compared with a corresponding serial implemented model. The comparison indicates that the parallel models provide a computation speed of 9-16 times faster than the serial one using Nvidia GeForce GT520M and Quadro 600 GPUs.","PeriodicalId":162311,"journal":{"name":"2015 IEEE Dallas Circuits and Systems Conference (DCAS)","volume":"91 1-2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114048245","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-12-17DOI: 10.1109/DCAS.2015.7356582
J. Ou
Previous studies have shown that the transconductance-to-drain-current ratio (gm/ID) based technique is useful for noise analysis and optimization of analog CMOS circuits. In this paper, we examine flicker noise closely and show that even though its slope (A) does not depend gm/ID parameters of a transistor, knowledge of gm/ID parameters is required in order to determine its slope accurately. We take a look at several scenarios that arise in practice, and generate a simple rule of thumb that simplifies the process of de-embedding the slope of flicker noise. Finally, we apply the results in the analysis of a micropower operational transconductance amplifier (OTA) and show that excellent agreement between simulation and analysis is achieved.
{"title":"Determination of transconductance-to-drain-current dependent flicker noise parameters","authors":"J. Ou","doi":"10.1109/DCAS.2015.7356582","DOIUrl":"https://doi.org/10.1109/DCAS.2015.7356582","url":null,"abstract":"Previous studies have shown that the transconductance-to-drain-current ratio (gm/ID) based technique is useful for noise analysis and optimization of analog CMOS circuits. In this paper, we examine flicker noise closely and show that even though its slope (A) does not depend gm/ID parameters of a transistor, knowledge of gm/ID parameters is required in order to determine its slope accurately. We take a look at several scenarios that arise in practice, and generate a simple rule of thumb that simplifies the process of de-embedding the slope of flicker noise. Finally, we apply the results in the analysis of a micropower operational transconductance amplifier (OTA) and show that excellent agreement between simulation and analysis is achieved.","PeriodicalId":162311,"journal":{"name":"2015 IEEE Dallas Circuits and Systems Conference (DCAS)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115516551","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-12-17DOI: 10.1109/DCAS.2015.7356590
Yiyan Li, R. J. Baker, Dominic Raad
A highly efficient and reliable electrowetting on dielectric (EWOD) digital microfluidics (DMF) chip is proposed. An 8 μm parylene C layer is used as the dielectric material. Extra vapor-phase silane (VPS) is introduced into the chamber and acts as an aerosol primer to enhance the chemical adhesion to the parylene C surface. The EWOD chip can perform droplet dispensing, merging and splitting smoothly in an air ambient. Dual electrode dispensing mode (DEDM) and single electrode dispensing mode (SEDM) are tested to investigate the dispensing volume accuracy. Small deviations (0.0467 μL for DEDM and 0.0303 μL for SEDM) are observed for the dispensing. Droplets from 1.5 μL to 2.3 μL are tested for the minimum splitting voltage. Larger droplets require larger voltages to be split. The proposed EWOD chip is promising for future point-of-care clinical diagnostics.
{"title":"A highly efficient and reliable electrowetting on dielectric device for point-of-care diagnostics","authors":"Yiyan Li, R. J. Baker, Dominic Raad","doi":"10.1109/DCAS.2015.7356590","DOIUrl":"https://doi.org/10.1109/DCAS.2015.7356590","url":null,"abstract":"A highly efficient and reliable electrowetting on dielectric (EWOD) digital microfluidics (DMF) chip is proposed. An 8 μm parylene C layer is used as the dielectric material. Extra vapor-phase silane (VPS) is introduced into the chamber and acts as an aerosol primer to enhance the chemical adhesion to the parylene C surface. The EWOD chip can perform droplet dispensing, merging and splitting smoothly in an air ambient. Dual electrode dispensing mode (DEDM) and single electrode dispensing mode (SEDM) are tested to investigate the dispensing volume accuracy. Small deviations (0.0467 μL for DEDM and 0.0303 μL for SEDM) are observed for the dispensing. Droplets from 1.5 μL to 2.3 μL are tested for the minimum splitting voltage. Larger droplets require larger voltages to be split. The proposed EWOD chip is promising for future point-of-care clinical diagnostics.","PeriodicalId":162311,"journal":{"name":"2015 IEEE Dallas Circuits and Systems Conference (DCAS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130144131","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-12-17DOI: 10.1109/DCAS.2015.7356591
Yiyan Li, R. J. Baker
The displacement of an intelligent PZT (piezoelectric materials based on modified lead zirconate titanate) controlled EWOD (electrowetting on dielectric) top plate is modeled by inverse Preisach hysteresis algorithm. First, the PZT deflection model is created from an experimental displacement dataset. The real time output is predicted based on the previously stored weighting functions. Upon the desired output and the current input, the input voltage is compensated by a feedforward voltage which is derived from the model using a closest match method. The feedforward process and the model are stored in a PC. A portable high voltage DAC (digital-to-analog converter) is used to drive the PZT cantilever structure. The worst-case DNL of the high voltage DAC is 0.8125 mV. The tracking errors of a 0.067 Hz triangle wave input are less than 5 μm. Results show the inverse Preisach model is a good candidate for precise EWOD top plate displacement hysteresis compensation.
{"title":"Precise EWOD top plate positioning using inverse Preisach model based hysteresis compensation","authors":"Yiyan Li, R. J. Baker","doi":"10.1109/DCAS.2015.7356591","DOIUrl":"https://doi.org/10.1109/DCAS.2015.7356591","url":null,"abstract":"The displacement of an intelligent PZT (piezoelectric materials based on modified lead zirconate titanate) controlled EWOD (electrowetting on dielectric) top plate is modeled by inverse Preisach hysteresis algorithm. First, the PZT deflection model is created from an experimental displacement dataset. The real time output is predicted based on the previously stored weighting functions. Upon the desired output and the current input, the input voltage is compensated by a feedforward voltage which is derived from the model using a closest match method. The feedforward process and the model are stored in a PC. A portable high voltage DAC (digital-to-analog converter) is used to drive the PZT cantilever structure. The worst-case DNL of the high voltage DAC is 0.8125 mV. The tracking errors of a 0.067 Hz triangle wave input are less than 5 μm. Results show the inverse Preisach model is a good candidate for precise EWOD top plate displacement hysteresis compensation.","PeriodicalId":162311,"journal":{"name":"2015 IEEE Dallas Circuits and Systems Conference (DCAS)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126464683","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-12-17DOI: 10.1109/DCAS.2015.7356593
Hari Chauhan, M. Onabajo, Martin McCormick, Vladimir Kvartenko, R. Coxe
Linearization techniques such as digital predistortion (DPD) are often employed to enhance the overall performance of power amplifiers (PAs). The specific performance requirements of a system typically depend on the application. For this reason, the implementation of a DPD technique after the fabrication of a PA can result in significant overhead cost. To ensure high performance with minimum cost prior to fabrication, it is beneficial to utilize a simulation method for design optimization of both the PA and the DPD. A simulation approach was developed to enable concurrent design optimizations of a PA along with its DPD algorithm using commercially available software. Simulation results obtained with a 10 W inverted Doherty power amplifier design and a DPD solution are presented to demonstrate the proposed approach.
{"title":"A simulation method for design and optimization of RF power amplifiers with digital predistortion","authors":"Hari Chauhan, M. Onabajo, Martin McCormick, Vladimir Kvartenko, R. Coxe","doi":"10.1109/DCAS.2015.7356593","DOIUrl":"https://doi.org/10.1109/DCAS.2015.7356593","url":null,"abstract":"Linearization techniques such as digital predistortion (DPD) are often employed to enhance the overall performance of power amplifiers (PAs). The specific performance requirements of a system typically depend on the application. For this reason, the implementation of a DPD technique after the fabrication of a PA can result in significant overhead cost. To ensure high performance with minimum cost prior to fabrication, it is beneficial to utilize a simulation method for design optimization of both the PA and the DPD. A simulation approach was developed to enable concurrent design optimizations of a PA along with its DPD algorithm using commercially available software. Simulation results obtained with a 10 W inverted Doherty power amplifier design and a DPD solution are presented to demonstrate the proposed approach.","PeriodicalId":162311,"journal":{"name":"2015 IEEE Dallas Circuits and Systems Conference (DCAS)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133248488","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-12-17DOI: 10.1109/DCAS.2015.7356598
Eran Pisek, S. Abu-Surra, R. Taori
A novel technique for Peak-to-Average Power Ratio (PAPR) reduction based on dithering is presented. The dithering method consists of adding a pre-defined random noise pattern to the transmitter time-domain Orthogonal Frequency Division Multiplexing (OFDM) symbol. The noise addition is performed to reduce the high peaks of the time-domain OFDM symbol. For each OFDM symbol, there is a process of selecting the most appropriate pre-defined noise pattern which achieves the lowest PAPR. We show that with merely 0.25 dB power increase to the time-domain transmitter OFDM signal, we attain the same Error-Vector Magnitude (EVM) in the receiver in different modulation schemes, with over 2 dB reduction in PAPR. The dithering information is transferred between the transmitter and the receiver using the pilot bits, thereby avoiding capacity reduction.
{"title":"Novel dithering-based peak-to-average power ratio reduction system","authors":"Eran Pisek, S. Abu-Surra, R. Taori","doi":"10.1109/DCAS.2015.7356598","DOIUrl":"https://doi.org/10.1109/DCAS.2015.7356598","url":null,"abstract":"A novel technique for Peak-to-Average Power Ratio (PAPR) reduction based on dithering is presented. The dithering method consists of adding a pre-defined random noise pattern to the transmitter time-domain Orthogonal Frequency Division Multiplexing (OFDM) symbol. The noise addition is performed to reduce the high peaks of the time-domain OFDM symbol. For each OFDM symbol, there is a process of selecting the most appropriate pre-defined noise pattern which achieves the lowest PAPR. We show that with merely 0.25 dB power increase to the time-domain transmitter OFDM signal, we attain the same Error-Vector Magnitude (EVM) in the receiver in different modulation schemes, with over 2 dB reduction in PAPR. The dithering information is transferred between the transmitter and the receiver using the pilot bits, thereby avoiding capacity reduction.","PeriodicalId":162311,"journal":{"name":"2015 IEEE Dallas Circuits and Systems Conference (DCAS)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127867503","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-12-17DOI: 10.1109/DCAS.2015.7356584
Angsuman Roy, R. J. Baker
A passive 2nd-order sigma-delta modulator using switched-capacitor based filters was designed, fabricated, and tested. A novel 2nd-order single feedback path topology is used. All circuitry is optimized for low power operation through the use of minimum size MOSFETs, component reduction and topology choice. The modulator was fabricated in On Semiconductor's C5 500-nm process. The implementation achieves a typical SNDR of above 50 dB for tested frequencies of 10 Hz to 3 kHz and has a peak SNDR of 57.8 dB, which corresponds to an ENOB of 9.3 bits. With a 2.5 V supply, the power consumption of the sigma-delta modulator is 6.75 μW. The modulator achieves a FOM of 1.78 pJ/step.
{"title":"A low-power switched-capacitor passive sigma-delta modulator","authors":"Angsuman Roy, R. J. Baker","doi":"10.1109/DCAS.2015.7356584","DOIUrl":"https://doi.org/10.1109/DCAS.2015.7356584","url":null,"abstract":"A passive 2nd-order sigma-delta modulator using switched-capacitor based filters was designed, fabricated, and tested. A novel 2nd-order single feedback path topology is used. All circuitry is optimized for low power operation through the use of minimum size MOSFETs, component reduction and topology choice. The modulator was fabricated in On Semiconductor's C5 500-nm process. The implementation achieves a typical SNDR of above 50 dB for tested frequencies of 10 Hz to 3 kHz and has a peak SNDR of 57.8 dB, which corresponds to an ENOB of 9.3 bits. With a 2.5 V supply, the power consumption of the sigma-delta modulator is 6.75 μW. The modulator achieves a FOM of 1.78 pJ/step.","PeriodicalId":162311,"journal":{"name":"2015 IEEE Dallas Circuits and Systems Conference (DCAS)","volume":"187 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115425524","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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