J. Lindstrand, C. Bryant, Markus Törmänen, H. Sjöland
{"title":"A 1.6–2.6GHz 29dBm injection-locked power amplifier with 64% peak PAE in 65nm CMOS","authors":"J. Lindstrand, C. Bryant, Markus Törmänen, H. Sjöland","doi":"10.1109/ESSCIRC.2011.6044966","DOIUrl":null,"url":null,"abstract":"This paper presents a wideband CMOS power amplifier intended for cellular handset applications. The circuit exploits injection locking to achieve a power gain of 20.5dB from a single stage amplifier. The maximum output power of 29dBm, with a peak drain- and power-added-efficiency (PAE) of 66% and 64%, respectively, occurs at a center frequency of 2GHz with a 3V supply. A cross-coupled cascode topology enables a wideband PAE exceeding 50% from 1.6 to 2.6GHz. For output power levels below 4dBm the circuit operates as a linear class AB amplifier with a power consumption of 17mW from a 0.48V supply. The power gain of 20.5dB is kept constant for all output powers; with an AM-AM- and AM-PM-conversion of 0.2dB and 17deg, respectively, over the entire WCDMA dynamic range of 80dB. The circuit is implemented in a standard 65nm CMOS process with a total chip area of 0.52×0.48mm2 including pads.","PeriodicalId":239979,"journal":{"name":"2011 Proceedings of the ESSCIRC (ESSCIRC)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"9","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2011 Proceedings of the ESSCIRC (ESSCIRC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSCIRC.2011.6044966","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 9
Abstract
This paper presents a wideband CMOS power amplifier intended for cellular handset applications. The circuit exploits injection locking to achieve a power gain of 20.5dB from a single stage amplifier. The maximum output power of 29dBm, with a peak drain- and power-added-efficiency (PAE) of 66% and 64%, respectively, occurs at a center frequency of 2GHz with a 3V supply. A cross-coupled cascode topology enables a wideband PAE exceeding 50% from 1.6 to 2.6GHz. For output power levels below 4dBm the circuit operates as a linear class AB amplifier with a power consumption of 17mW from a 0.48V supply. The power gain of 20.5dB is kept constant for all output powers; with an AM-AM- and AM-PM-conversion of 0.2dB and 17deg, respectively, over the entire WCDMA dynamic range of 80dB. The circuit is implemented in a standard 65nm CMOS process with a total chip area of 0.52×0.48mm2 including pads.