Analog circuit design at and below VT + 2Vds,sat

Abstract

Design methods and architectures for high-performance analog circuitry which operates at supply voltages at and below VT + 2 Vds,sat are developed. A low voltage amplifier is designed using these methods. The amplifier, fabricated in an AMIS 0.5 mum CMOS process with 0.8 V p-channel threshold voltages, is shown to operate at supply voltages as low as 0.75 V with full rail-to-rail input and output operation. The amplifier shows 105 dB of open loop gain and GBW of 0.31 MHz while dissipating 11.5 muW from a 0.8 V supply. The design methods may be used with advanced CMOS processes to further reduce the required analog supply voltage.