Design and Analysis of Current Starved VCO Targeting SCL 180 nm CMOS Process

Abstract

This paper presents a low power 5-stage current starved voltage controlled oscillator, designed at 50 MHz. For control voltage varying from 0.4 V to 1.6 V, the oscillator frequency linearly varies from 7 MHz to 105 MHz linearly. At supply voltage of 1.8 V, the circuit is low power (134 µW) in comparison to circuits reported in the literature. It exhibits a phase noise of -101.9 dBc/Hz at 1 MHz offset from 50 MHz carrier frequency. The circuit is designed in SCL 180 nm CMOS process using cadence environment.