Circuit architecture and measurement technique to reduce the leakage current stemming from peripheral circuits with an array structure in examining the resistive element

Abstract

A circuit architecture and measurement technique are proposed to reduce the leakage current that passes through peripheral circuits when examining arrays of resistive elements. We reveal, with the aid of circuit simulations, that high resolution measurements of resistive elements can be realized with the stacked column-selection array and the addition of a leakage-control terminal.