Pub Date : 2015-03-23DOI: 10.1109/ICMTS.2015.7106119
David Chen, G. Lin, Tien Hua Lee, Ryan Lee, Y. C. Liu, Meng Fan Wang, Yi Ching Cheng, D. Y. Wu
We successfully developed and verified a complete compact model solution for layout dependent effect (LDE) of FinFET technology. LDE has significant impact on the device performances mainly due to the application of stressors and aggressive device scaling. With LDE, performance degradation may be up to 10% or more. In this work, compact model solution for Length of Oxidation (LOD), Well Proximity Effect (WPE), Neighboring Diffusion Effect (NDE), Metal Boundary Effect (MBE), and Gate Line End Effect (GLE) were delivered. This solution was implemented successfully in BSIM-CMG for efficient circuit simulation.
{"title":"Compact modeling solution of layout dependent effect for FinFET technology","authors":"David Chen, G. Lin, Tien Hua Lee, Ryan Lee, Y. C. Liu, Meng Fan Wang, Yi Ching Cheng, D. Y. Wu","doi":"10.1109/ICMTS.2015.7106119","DOIUrl":"https://doi.org/10.1109/ICMTS.2015.7106119","url":null,"abstract":"We successfully developed and verified a complete compact model solution for layout dependent effect (LDE) of FinFET technology. LDE has significant impact on the device performances mainly due to the application of stressors and aggressive device scaling. With LDE, performance degradation may be up to 10% or more. In this work, compact model solution for Length of Oxidation (LOD), Well Proximity Effect (WPE), Neighboring Diffusion Effect (NDE), Metal Boundary Effect (MBE), and Gate Line End Effect (GLE) were delivered. This solution was implemented successfully in BSIM-CMG for efficient circuit simulation.","PeriodicalId":177627,"journal":{"name":"Proceedings of the 2015 International Conference on Microelectronic Test Structures","volume":"105 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116301809","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-03-23DOI: 10.1109/ICMTS.2015.7106117
A. Padovani, L. Larcher, L. Vandelli, M. Bertocchi, R. Cavicchioli, D. Veksler, G. Bersuker
We present a comprehensive simulation framework to interpret electrical characteristics (I-V, C-V, G-V, Charge-Pumping, BTI, CVS, RVS, ...) commonly used for material characterization and reliability analysis of gate dielectric stacks in modern semiconductor devices. By accounting for the physical processes controlling charge transport through the dielectric (e.g. carrier trapping/de-trapping at the defect sites, defect generation, etc.), which is modeled using a novel approach based of material characteristics [1], [2], the simulations provide a unique link between the electrical measurements data and specific atomic defects in the dielectric stack. Within this methodology, the software allows an accurate defect spectroscopy by cross-correlating measurements of pre-stress electrical parameters (IV, CV, BTI). These data are then used to project the stack reliability through the simulations of stress-induced leakage current (SILC) and time-dependent dielectric degradation trends, demonstrating the tool capabilities as a technology characterization/optimization benchmark.
{"title":"Cross-correlation of electrical measurements via physics-based device simulations: Linking electrical and structural characteristics","authors":"A. Padovani, L. Larcher, L. Vandelli, M. Bertocchi, R. Cavicchioli, D. Veksler, G. Bersuker","doi":"10.1109/ICMTS.2015.7106117","DOIUrl":"https://doi.org/10.1109/ICMTS.2015.7106117","url":null,"abstract":"We present a comprehensive simulation framework to interpret electrical characteristics (I-V, C-V, G-V, Charge-Pumping, BTI, CVS, RVS, ...) commonly used for material characterization and reliability analysis of gate dielectric stacks in modern semiconductor devices. By accounting for the physical processes controlling charge transport through the dielectric (e.g. carrier trapping/de-trapping at the defect sites, defect generation, etc.), which is modeled using a novel approach based of material characteristics [1], [2], the simulations provide a unique link between the electrical measurements data and specific atomic defects in the dielectric stack. Within this methodology, the software allows an accurate defect spectroscopy by cross-correlating measurements of pre-stress electrical parameters (IV, CV, BTI). These data are then used to project the stack reliability through the simulations of stress-induced leakage current (SILC) and time-dependent dielectric degradation trends, demonstrating the tool capabilities as a technology characterization/optimization benchmark.","PeriodicalId":177627,"journal":{"name":"Proceedings of the 2015 International Conference on Microelectronic Test Structures","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133538299","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-03-23DOI: 10.1109/ICMTS.2015.7106106
Garry Moore, J. Liao, Scott McDade, B. Verzi
This paper will look at both technical and business advantages of parallel vs. serial inline parametric testing, secondary effects of changing test strategies, quantifying return on investment of newer test strategies, and next steps in pushing the envelope of test. Topics such as cost, schedule, macro design and quality will be explored to understand tradeoffs and synergies of test strategies. Examples and metrics of parallel compared to serial testing will be examined.
{"title":"Accelerating 14nm device learning and yield ramp using parallel test structures as part of a new inline parametric test strategy","authors":"Garry Moore, J. Liao, Scott McDade, B. Verzi","doi":"10.1109/ICMTS.2015.7106106","DOIUrl":"https://doi.org/10.1109/ICMTS.2015.7106106","url":null,"abstract":"This paper will look at both technical and business advantages of parallel vs. serial inline parametric testing, secondary effects of changing test strategies, quantifying return on investment of newer test strategies, and next steps in pushing the envelope of test. Topics such as cost, schedule, macro design and quality will be explored to understand tradeoffs and synergies of test strategies. Examples and metrics of parallel compared to serial testing will be examined.","PeriodicalId":177627,"journal":{"name":"Proceedings of the 2015 International Conference on Microelectronic Test Structures","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126839493","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-03-23DOI: 10.1109/ICMTS.2015.7106101
Lin You, J. Ahn, Emily Hitz, J. Michelson, Y. Obeng, J. Kopanski
A test chip to produce known and controllable gradients of surface potential and magnetic field at the chip surface and suitable for imaging with various types of scanning probe microscopes is presented. The purpose of the test chip is to evaluate various SPMs as metrology tools to image electro-magnetic fields within nanoelectronic devices and multi-level interconnects, and as metrology tools to detect defects in back end of line (BEOL) metallization and packaging processes. Four different levels of metal are used to create different buried structures that, when biased, will produce varying electric field and magnetic field distributions. Contacts to the chip are made via wire bonds to a printed circuit board (PCB) that allows programed external biases and ground to be applied to specific metal levels while imaging with a SPM. DC and high frequency COMSOL simulations of the test structures were conducted to determine the expected field distributions. Electric field can be imaged via scanning Kelvin force microscopy (SKFM); magnetic field via scanning magnetic force microscopy (MFM); and the capacitance of buried metal lines via scanning microwave microscopy (SMM). The combination of precisely known structures and accurate simulations will allow the spatial resolution and accuracy of various SPMs sensitive to electric field (potential) or magnetic field to be determined and improved.
{"title":"Electromagnetic field test structure chip for back end of the line metrology","authors":"Lin You, J. Ahn, Emily Hitz, J. Michelson, Y. Obeng, J. Kopanski","doi":"10.1109/ICMTS.2015.7106101","DOIUrl":"https://doi.org/10.1109/ICMTS.2015.7106101","url":null,"abstract":"A test chip to produce known and controllable gradients of surface potential and magnetic field at the chip surface and suitable for imaging with various types of scanning probe microscopes is presented. The purpose of the test chip is to evaluate various SPMs as metrology tools to image electro-magnetic fields within nanoelectronic devices and multi-level interconnects, and as metrology tools to detect defects in back end of line (BEOL) metallization and packaging processes. Four different levels of metal are used to create different buried structures that, when biased, will produce varying electric field and magnetic field distributions. Contacts to the chip are made via wire bonds to a printed circuit board (PCB) that allows programed external biases and ground to be applied to specific metal levels while imaging with a SPM. DC and high frequency COMSOL simulations of the test structures were conducted to determine the expected field distributions. Electric field can be imaged via scanning Kelvin force microscopy (SKFM); magnetic field via scanning magnetic force microscopy (MFM); and the capacitance of buried metal lines via scanning microwave microscopy (SMM). The combination of precisely known structures and accurate simulations will allow the spatial resolution and accuracy of various SPMs sensitive to electric field (potential) or magnetic field to be determined and improved.","PeriodicalId":177627,"journal":{"name":"Proceedings of the 2015 International Conference on Microelectronic Test Structures","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122282668","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-03-23DOI: 10.1109/ICMTS.2015.7106137
E. Sirotkin, S. Smith, R. Walker, J. Terry, A. Walton
This paper presents a method of electrically determining the permeability of patterned electroplated structures and brings together the simultaneous wafer mapping of magnetic permeability, electrical resistivity and mechanical strain of electroplated ferromagnetic films together with the thickness of the films and their composition. The wafer mapping of all these properties is implemented using set of simple automated electrical and optical techniques that facilitates the spatial correlation between different parameters. This enables the uniformity of the electrodeposited conductive ferromagnetic films to be analyzed and supports the optimization of both their properties and the technological processes associated with their deposition.
{"title":"Test structures for the wafer mapping and correlation of electrical, mechanical and high frequency magnetic properties of electroplated ferromagnetic alloy films","authors":"E. Sirotkin, S. Smith, R. Walker, J. Terry, A. Walton","doi":"10.1109/ICMTS.2015.7106137","DOIUrl":"https://doi.org/10.1109/ICMTS.2015.7106137","url":null,"abstract":"This paper presents a method of electrically determining the permeability of patterned electroplated structures and brings together the simultaneous wafer mapping of magnetic permeability, electrical resistivity and mechanical strain of electroplated ferromagnetic films together with the thickness of the films and their composition. The wafer mapping of all these properties is implemented using set of simple automated electrical and optical techniques that facilitates the spatial correlation between different parameters. This enables the uniformity of the electrodeposited conductive ferromagnetic films to be analyzed and supports the optimization of both their properties and the technological processes associated with their deposition.","PeriodicalId":177627,"journal":{"name":"Proceedings of the 2015 International Conference on Microelectronic Test Structures","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122952334","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-03-23DOI: 10.1109/ICMTS.2015.7106103
T. Umeda, Y. Hirano, D. Suzuki, A. Tone, T. Inoue, H. Kikuchihara, M. Miura-Mattausch, H. Mattausch
The additional channel-dopant layer of normally-on MOSFETs leads to accumulation-layer current near channel surface and deeper-lying neutral-region current above the p/n junction, which dominate bias conditions above and below flat-band, respectively. The developed compact model accurately captures these currents and exploits their different bias-condition properties for efficient parameter extraction.
{"title":"Compact modeling and parameter extraction strategy of normally-on MOSFET","authors":"T. Umeda, Y. Hirano, D. Suzuki, A. Tone, T. Inoue, H. Kikuchihara, M. Miura-Mattausch, H. Mattausch","doi":"10.1109/ICMTS.2015.7106103","DOIUrl":"https://doi.org/10.1109/ICMTS.2015.7106103","url":null,"abstract":"The additional channel-dopant layer of normally-on MOSFETs leads to accumulation-layer current near channel surface and deeper-lying neutral-region current above the p/n junction, which dominate bias conditions above and below flat-band, respectively. The developed compact model accurately captures these currents and exploits their different bias-condition properties for efficient parameter extraction.","PeriodicalId":177627,"journal":{"name":"Proceedings of the 2015 International Conference on Microelectronic Test Structures","volume":"266 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130852192","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-03-23DOI: 10.1109/ICMTS.2015.7106116
Y. Li, J. Terry, S. Smith, A. Walton, G. McHale, B. Xu
This paper reports on the sensing of large strain using a mechanically actuated switch gate and a variable resistor surface creasing test structure. Test structures with different gate and interconnect/wiring geometries have been designed, fabricated and characterised. They respond to designed strain values with a reduction in device resistivity of 11 to 12 orders of magnitude. Results from strain measurements ranging from 0.2 to 0.6 are reported for test structures with electrode spaces of 10 to 60 μm.
{"title":"Elastic instabilities induced large surface strain sensing structures (EILS)","authors":"Y. Li, J. Terry, S. Smith, A. Walton, G. McHale, B. Xu","doi":"10.1109/ICMTS.2015.7106116","DOIUrl":"https://doi.org/10.1109/ICMTS.2015.7106116","url":null,"abstract":"This paper reports on the sensing of large strain using a mechanically actuated switch gate and a variable resistor surface creasing test structure. Test structures with different gate and interconnect/wiring geometries have been designed, fabricated and characterised. They respond to designed strain values with a reduction in device resistivity of 11 to 12 orders of magnitude. Results from strain measurements ranging from 0.2 to 0.6 are reported for test structures with electrode spaces of 10 to 60 μm.","PeriodicalId":177627,"journal":{"name":"Proceedings of the 2015 International Conference on Microelectronic Test Structures","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130071574","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-03-23DOI: 10.1109/ICMTS.2015.7106094
T. Kane
14nm BEOL (back end of line) TDDB (time to dielectric defect breakdown) test site structures successfully detect reliability defects but pose significant challenges in defect analysis At these advanced technology nodes, the reduction in copper land cross sectional area is accompanied by increased current density and electromigration failure rates. TDDB reliability test structures must be sensitive to capturing reliability defects. These same TDDB test site structures combined with porous ultra low-k (ULK) dielectric films represent real challenges in localizing and then determining BEOL reliability defects. Defect localization is difficult due to the complexity of these multiple metal layers along with the presence of the porous, low k dielectric films which exhibit shrinkage or void formation when exposed to an e-beam/FIB ion beam > 1 keV. Due to the porosity of these ULK dielectric films, they are especially susceptible to gallium ion implantation. It has been reported elsewhere that suppressing copper diffusion at the copper land/cap interface can be achieved by depositing a thin layer of CoWP and doping the copper seed layer with manganese [15, 16, 17]. However, a method for analytically confirming that these approaches for suppressing the copper diffusion do not affect TDDB performance/electromigration behavior must be demonstrated.
{"title":"14nm BEOL TDDB reliability testing and defect analysis","authors":"T. Kane","doi":"10.1109/ICMTS.2015.7106094","DOIUrl":"https://doi.org/10.1109/ICMTS.2015.7106094","url":null,"abstract":"14nm BEOL (back end of line) TDDB (time to dielectric defect breakdown) test site structures successfully detect reliability defects but pose significant challenges in defect analysis At these advanced technology nodes, the reduction in copper land cross sectional area is accompanied by increased current density and electromigration failure rates. TDDB reliability test structures must be sensitive to capturing reliability defects. These same TDDB test site structures combined with porous ultra low-k (ULK) dielectric films represent real challenges in localizing and then determining BEOL reliability defects. Defect localization is difficult due to the complexity of these multiple metal layers along with the presence of the porous, low k dielectric films which exhibit shrinkage or void formation when exposed to an e-beam/FIB ion beam > 1 keV. Due to the porosity of these ULK dielectric films, they are especially susceptible to gallium ion implantation. It has been reported elsewhere that suppressing copper diffusion at the copper land/cap interface can be achieved by depositing a thin layer of CoWP and doping the copper seed layer with manganese [15, 16, 17]. However, a method for analytically confirming that these approaches for suppressing the copper diffusion do not affect TDDB performance/electromigration behavior must be demonstrated.","PeriodicalId":177627,"journal":{"name":"Proceedings of the 2015 International Conference on Microelectronic Test Structures","volume":"144 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121999698","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-03-23DOI: 10.1109/ICMTS.2015.7106118
Cory Compton
A set of NPN CML (Current Mode Logic) oscillators is designed in a 0.18um SiGe BiCMOS process, with the intention to provide model verification and process monitoring capabilities. The main design goals are that the oscillators need to be small and easy to test such that many of them can be placed in the scribe line and be measured by production PCM test equipment.
{"title":"NPN CML ring oscillators for model verification and process monitoring","authors":"Cory Compton","doi":"10.1109/ICMTS.2015.7106118","DOIUrl":"https://doi.org/10.1109/ICMTS.2015.7106118","url":null,"abstract":"A set of NPN CML (Current Mode Logic) oscillators is designed in a 0.18um SiGe BiCMOS process, with the intention to provide model verification and process monitoring capabilities. The main design goals are that the oscillators need to be small and easy to test such that many of them can be placed in the scribe line and be measured by production PCM test equipment.","PeriodicalId":177627,"journal":{"name":"Proceedings of the 2015 International Conference on Microelectronic Test Structures","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125681901","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-03-23DOI: 10.1109/ICMTS.2015.7106122
Y. Ogasahara, M. Hioki, T. Nakagawa, T. Sekigawa, T. Tsutsumi, H. Koike
This paper demonstrates notable impact of Vth shift due to STI-induced dopant redistribution on ultra-low voltage designs. 2.5X Ion change at ultra-low voltages due to STI was measured on a 65nm SOTB CMOS process. Serious 6X Ion change due to inverse narrow channel effects was also observed. We propose ring oscillator based measurement procedure observing Vth shift by exploiting flexible Vth controllability by backgate biasing of SOTB process.
{"title":"Measurement of Vth variation due to STI stress and inverse narrow channel effect at ultra-low voltage in a variability-suppressed process","authors":"Y. Ogasahara, M. Hioki, T. Nakagawa, T. Sekigawa, T. Tsutsumi, H. Koike","doi":"10.1109/ICMTS.2015.7106122","DOIUrl":"https://doi.org/10.1109/ICMTS.2015.7106122","url":null,"abstract":"This paper demonstrates notable impact of V<sub>th</sub> shift due to STI-induced dopant redistribution on ultra-low voltage designs. 2.5X I<sub>on</sub> change at ultra-low voltages due to STI was measured on a 65nm SOTB CMOS process. Serious 6X I<sub>on</sub> change due to inverse narrow channel effects was also observed. We propose ring oscillator based measurement procedure observing V<sub>th</sub> shift by exploiting flexible V<sub>th</sub> controllability by backgate biasing of SOTB process.","PeriodicalId":177627,"journal":{"name":"Proceedings of the 2015 International Conference on Microelectronic Test Structures","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125110731","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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