H. Yamagata, S. Yanagawa, T. Komoto, M. Bairo, Y. Kiyota, S. Yoneda, M. Oishi, A. Kuranouchi, C. Arai
{"title":"101 GHz f/sub Tmax/ SiGe:C HBT integrated into 0.25 /spl mu/m CMOS with conventional LOCOS isolation","authors":"H. Yamagata, S. Yanagawa, T. Komoto, M. Bairo, Y. Kiyota, S. Yoneda, M. Oishi, A. Kuranouchi, C. Arai","doi":"10.1109/ESSDER.2004.1356524","DOIUrl":null,"url":null,"abstract":"A low-complexity but high-performance SiGe:C BiCMOS technology is realized by conventional simple LOCOS isolation and non-selective SiGe:C epitaxy with optimized impurity profiles. Stress-induced misfit dislocations found in the SiGe:C layer on LOCOS-patterned wafers were successfully eliminated by optimizing the epitaxial process. This, in combination with optimization of HBT impurity profiles, produced a 99% yield of 10000 parallel arrays with an f/sub Tmax/ of 101 GHz. The HBT has been successfully integrate in a 0.25 /spl mu/m CMOS with passive components, which is suitable for low-cost RF mixed-signal applications.","PeriodicalId":287103,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSDER.2004.1356524","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
A low-complexity but high-performance SiGe:C BiCMOS technology is realized by conventional simple LOCOS isolation and non-selective SiGe:C epitaxy with optimized impurity profiles. Stress-induced misfit dislocations found in the SiGe:C layer on LOCOS-patterned wafers were successfully eliminated by optimizing the epitaxial process. This, in combination with optimization of HBT impurity profiles, produced a 99% yield of 10000 parallel arrays with an f/sub Tmax/ of 101 GHz. The HBT has been successfully integrate in a 0.25 /spl mu/m CMOS with passive components, which is suitable for low-cost RF mixed-signal applications.
京公网安备 11010802042870号
京ICP备2023020795号-1
分享
求助内容：
应助结果提醒方式：
扫码关注我们
