Design of an LVCMOS high resolution frequency synthesizer

Abstract

This work presents the design and implementation of a high frequency high resolution clock synthesizer. A phased-locked-loop (PLL) with internal feedback is the core of the synthesizer. The operating frequency range of the PLL oscillator is 1 GHz to 2 GHz. High resolution is achieved by a wide range programmable feedback divider from 1 to 1024 divide factors in steps of 1. A programmable current mode charge pump is designed to manage the wide range feedback divider. Circuit simulation results demonstrate design feasibility. The design was implemented on a 0.18 /spl mu/m low voltage CMOS (LVCMOS) technology.