{"title":"CR5M: A mirroring-powered channel-RAID5 architecture for an SSD","authors":"Yu Wang, Wei Wang, T. Xie, Wen Pan, Yanyan Gao, Yiming Ouyang","doi":"10.1109/MSST.2014.6855547","DOIUrl":null,"url":null,"abstract":"Manufacturers are continuously pushing NAND flash memory into smaller geometries and enforce each cell to store multiple bits in order to largely reduce its cost. Unfortunately, these scaling down techniques inherently degrade the endurance and reliability of flash memory. As a result, permanent errors such as block or die failures could occur with a higher possibility. While most transient errors like programming errors can be fixed by an ECC (error correction code) scheme, rectifying permanent errors requires a data redundancy mechanism like RAID (redundant array of independent disks) in a single SSD where multiple channels work in parallel. To enhance the reliability of a solid-state drive (SSD) while maintaining its performance, we first implement several common RAID structures in the channel level of a single SSD to understand their impact on an SSD's performance. Next, we propose a new data redundancy architecture called CR5M (Channel-RAID5 with Mirroring), which can be applied to one SSD for mission-critical applications. CR5M utilizes hidden mirror chips to accelerate the performance of small writes. Finally, we conduct extensive simulations using real-world traces and synthetic benchmarks on a validated simulator to evaluate CR5M. Experimental results demonstrate that compared with CR5 (Channel-RAID5) CR5M decreases mean response time by up to 25.8%. Besides, it reduces the average writes per channel by up to 23.6%.","PeriodicalId":188071,"journal":{"name":"2014 30th Symposium on Mass Storage Systems and Technologies (MSST)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2014-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"16","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2014 30th Symposium on Mass Storage Systems and Technologies (MSST)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MSST.2014.6855547","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 16
Abstract
Manufacturers are continuously pushing NAND flash memory into smaller geometries and enforce each cell to store multiple bits in order to largely reduce its cost. Unfortunately, these scaling down techniques inherently degrade the endurance and reliability of flash memory. As a result, permanent errors such as block or die failures could occur with a higher possibility. While most transient errors like programming errors can be fixed by an ECC (error correction code) scheme, rectifying permanent errors requires a data redundancy mechanism like RAID (redundant array of independent disks) in a single SSD where multiple channels work in parallel. To enhance the reliability of a solid-state drive (SSD) while maintaining its performance, we first implement several common RAID structures in the channel level of a single SSD to understand their impact on an SSD's performance. Next, we propose a new data redundancy architecture called CR5M (Channel-RAID5 with Mirroring), which can be applied to one SSD for mission-critical applications. CR5M utilizes hidden mirror chips to accelerate the performance of small writes. Finally, we conduct extensive simulations using real-world traces and synthetic benchmarks on a validated simulator to evaluate CR5M. Experimental results demonstrate that compared with CR5 (Channel-RAID5) CR5M decreases mean response time by up to 25.8%. Besides, it reduces the average writes per channel by up to 23.6%.
为了大幅降低成本,制造商们不断地将NAND闪存推向更小的几何形状,并强制每个单元存储多个比特。不幸的是,这些缩小技术本质上降低了闪存的耐用性和可靠性。因此,诸如块或模具失效之类的永久性错误可能会以更高的可能性发生。虽然大多数瞬时错误(如编程错误)可以通过ECC(错误纠正码)方案修复,但纠正永久性错误需要在单个SSD中使用数据冗余机制,如RAID(独立磁盘冗余阵列),其中多个通道并行工作。为了提高固态硬盘的可靠性,同时保持其性能,我们首先在单个SSD的通道级别实现几种常见的RAID结构,以了解它们对SSD性能的影响。接下来,我们提出一种新的数据冗余架构,称为CR5M (Channel-RAID5 with Mirroring),它可以应用于一个SSD,用于任务关键型应用程序。CR5M利用隐藏镜像芯片来加速小写的性能。最后,我们在经过验证的模拟器上使用真实世界的轨迹和合成基准进行了广泛的模拟,以评估CR5M。实验结果表明,与CR5 (Channel-RAID5)相比,CR5M的平均响应时间降低了25.8%。此外,它还将每个通道的平均写操作减少了23.6%。