Hierarchical concepts in the design of processor arrays

CompEuro 1992 Proceedings Computer Systems and Software Engineering Pub Date : 1992-05-04 DOI:10.1109/CMPEUR.1992.218504

U. Arzt, J. Teich, M. Schumacher, L. Thiele

引用次数: 4

Abstract

A hierarchical representation of parallel algorithms is described that can be systematically mapped onto a class of massive parallel architectures called processor arrays. A notation of hierarchical parallel programs is introduced for the representation of algorithms that can be mapped onto processor arrays. By means of a transformative approach, two provably correct program transformations are introduced to solve the problems of generating (CREATE) and of dissolving (FLATTEN) different levels of hierarchy. The program transformations CREATE and FLATTEN are formally described and explained by an example.<>

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处理器阵列设计中的层次概念

描述了并行算法的分层表示，可以系统地映射到一类称为处理器阵列的大规模并行体系结构。为了表示可以映射到处理器阵列上的算法，引入了分层并行程序的表示法。通过转换方法，引入了两种可证明正确的程序转换来解决不同层次结构的生成(CREATE)和分解(FLATTEN)问题。对程序转换CREATE和FLATTEN进行了形式化描述，并通过实例进行了解释。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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CompEuro 1992 Proceedings Computer Systems and Software Engineering

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