Malgorzata Rechmal-Lesse, Gerald Alexander Koroa, Y. G. Adhisantoso, M. Olbrich
{"title":"Automated Model Generation Including Variations for Formal Verification of Nonlinear Analog Circuits","authors":"Malgorzata Rechmal-Lesse, Gerald Alexander Koroa, Y. G. Adhisantoso, M. Olbrich","doi":"10.1109/newcas49341.2020.9159822","DOIUrl":null,"url":null,"abstract":"With the advancements in analog/mixed-signal (AMS) systems and continuously shrinking design sizes, there is an increased demand for reliable verification to ensure correct behavior. To overcome this obstacle, using formal verification is a promising option. We present a modeling system that automatically provides dependable set-valued models from circuit netlists in a form suitable for reachability analysis. Our method is based on local linearizations of the nonlinear circuit. Linearized locations are computed on-the-fly depending on which states are reachable to avoid the state-space explosion problem. The set-valued models include device parameter variations, modeling errors and uncertain input stimuli.","PeriodicalId":135163,"journal":{"name":"2020 18th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2020 18th IEEE International New Circuits and Systems Conference (NEWCAS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/newcas49341.2020.9159822","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
With the advancements in analog/mixed-signal (AMS) systems and continuously shrinking design sizes, there is an increased demand for reliable verification to ensure correct behavior. To overcome this obstacle, using formal verification is a promising option. We present a modeling system that automatically provides dependable set-valued models from circuit netlists in a form suitable for reachability analysis. Our method is based on local linearizations of the nonlinear circuit. Linearized locations are computed on-the-fly depending on which states are reachable to avoid the state-space explosion problem. The set-valued models include device parameter variations, modeling errors and uncertain input stimuli.