Compact reliability model for degradation of advanced p-MOSFETs due to NBTI and hot-carrier effects in the circuit simulation

Abstract

A compact reliability model is reported, which includes both the channel hot carrier (CHC) and the negative bias thermal instability (NBTI) effects in p-MOSFETs. The developed compact NBTI model, which describes both interface-state generation and hole-trapping mechanisms, is further improved by considering additionally the impact of the drain bias Vds. With increased Vds, the NBTI effect is weakened due to the reduction of the vertical gate oxide field, and the CHC effect is enhanced by the increased lateral channel electric field. Therefore, the threshold voltage is observed to decrease in the low Vds regime, and then increases again in the high Vds regime. Such “turn-around” characteristic is correctly modeled using the improved compact NBTI model. Implementation of this reliability model into the surface-potential-based compact model HiSIM enables accurate prediction of the CHC enhanced NBTI degradation for wide ranges of time duration and bias conditions. This allows real-time simulation for the circuit-performance degradation occurring during actual circuit operation.