Detecting positive voltage attacks on CMOS circuits

Abstract

This work investigates voltage attacks over the nominal voltage on CMOS digital circuits designed on advanced technology nodes. The behavior of both combinatorial and sequential logic is analyzed in presence of static and dynamic overvoltage attacks. It points out that only modifications of propagation delays occur in presence of such attacks. Timing detection circuits are then introduced to detect hold violations. These circuits offer good performance with low area overhead but their implementation require extra timing constraints on the design to protect. In addition, multiple power domain circuits must be considered to thwart overpowering attacks.