An area-efficient ternary full adder using hybrid SET-MOS technology

Abstract

This paper presents a novel design of ternary full adder (TFA) using hybrid single-electron transistor (SET) and MOS technology. The proposed circuit is evaluated using the Cadence Spectre simulator with 180nm CMOS technology and SET macro models under various test conditions. Results show that the proposed TFA dramatically reduces the number of transistors required with little or no loss in energy efficiency.