0.9 V DSP blocks: a 15 ns 4 K SRAM and a 45 ns 16-bit multiply/accumulator

Abstract

4 K SRAM and 16 bit multiply/accumulate DSP blocks have been designed and fabricated in Complementary heterostructure GaAs. Both circuits operate from 1.5 V to below 0.9 V. The SRAM uses 28,272 transistors in an area of 2.44 mm/sup 2/. Cell size is 278 /spl mu/m/sup 2/ at 1.0 /spl mu/m gate length. Measured results show an access delay of 5.3 ns at 1.5 V and 15.0 ns at 0.9 V. At 0.9 V, total power is 0.36 mW. The CGaAs multiplier uses a 16-bit modified Booth architecture with a 3-way 40-bit accumulator. The multiplier uses 11,200 transistors in an area of 1.23 mm/sup 2/. Measured delay is 19.0 ns at 1.5 V and 44.7 ns at 0.9 V. At 0.9 V, total current is less than 0.4 mA.