Chip-scale cooling of power semiconductor devices: Fabrication of Jet impingement design

Abstract

Chip-scale cooling is proposed for future wide bandgap (WBG) power semiconductor devices to overcome challenges associated with device power dissipation, high heat fluxes up to 1 kW/cm2, and traditional package thermal resistance. In the current paper, fabrication of a chip-scale cooler that utilizes fluid jet impingement plus flow through an optimized branching microchannel topology is described. This chip-scale cooling structure is expected to provide an estimated 70% higher cooling performance for the same pumping power and more uniform cooling relative to a straight microchannel design based on prior numerical and experimental studies. The proposed embedded flow structure is defined by three layers, and each layer is fabricated by double-sided etching of a six-inch silicon wafer. The final device is obtained by bonding the three etched layers together and dicing the three-wafer stack into individual chips. The design and fabrication of the cooling chip, including process challenges and solutions, is the focus of the current paper. Discussion of the current technology and a vision of its future application is also provided.