Advanced modelling and parameter extraction of the MOSFET ESD breakdown triggering in the 90nm CMOS node technologies

Abstract

The electro-static discharge (ESD) breakdown mechanism of 90 nm MOSFET n+/pwell devices is described in detail and modelled with a physics based equation set. The newly developed consistent parameter extraction approach allows to overcome the limitations of existing methodologies, which are not applicable for the 90 nm CMOS node device behaviour, and to calibrate precisely the snapback models. These models will help optimising the ESD robust I/O cells, which use 90 nm MOSFET devices as I/O drivers and ESD structures.