Improving Multi-Context Execution Speed on DRFPGAs

Abstract

To implement a user circuit on a Dynamically Reconflgurable FPGA (DRFPGA) the circuit needs to be temporally partitioned into several sub-circuits such that their sequential execution on the DRFPGA yields the same result as that of the user circuit. In devices where interconnect delay is far dominating than logic delay, such implementation has the prospect of executing user circuits faster than traditional FPGA implementation, since temporal partitioning divides a long spatial wire of a circuit into several short temporal wires, thus converting interconnect delay into logic delay. To realize such prospect, reconfiguration delay and temporal communication delay of a DRFPGA must be kept as low as possible. This paper studies these issues and reports the architecture and performance of Flexible Processor III (FP3), a newly proposed DRFPGA. FP3 employs a new shift register type temporal interconnect and Nearest Neighbor (NN) type spatial interconnect to reduce the delay mentioned above. Correct behavior of FP3, designed and fabricated in 0.35 um CMOS technology, has been confirmed and our experimental results show that there exist cases where the best user circuit speed is achieved when two or more contexts are in use.