Mitigating the effects of the dut interface board and test system parasitics in gigabit-plus measurements

Abstract

This paper discusses the issues associated causing jitter in the measurement path can be well with removing the effects of the measurement path characterized and simulated, simple methods of in very high speed measurements. Of critical compensating for measurement path error cannot be concern is deterministic jitter caused by the applied. This paper explores this issue and suggests interaction between the measurement path and the two complementary solutions for addressing such device under test. While individual components jitter.