VHDL design environment for legacy electronics (VDELE)

Abstract

The rapidly escalating DMS (Diminishing Manufacturing Sources) problem for digital electronic components is seriously impacting the ability of avionics equipment suppliers to provide affordable equipment to new aircraft. Sustainment of this equipment in the field is a major cost driver in the O&S (Operation & Support) cost equation due to the same problem. The development of F/sup 3/I (Form-Fit-Function-Interface) printed circuit assembly (PCA) level replacements for obsolete digital electronics provides the opportunity to solve both of these problems at minimum cost. The Wright Laboratories sponsored VDELE (VHDL Design Environment for Legacy Electronics) project has developed innovative methodologies for the development of F/sup 3/I clones for PCAs that have become obsolete due to DMS problems. The VDELE process extracts VHDL model and test information from the customer digital database and then applies commercially available tools to refine and validate the model in a virtual development environment. The refined VHDL simulation model is then provided to a qualified supplier in the form of a technology independent executable specification for synthesis into a clone PCA replacement. We present a brief description of the VDELE process and the application of the VDELE methodologies to the development of an FPGA (field programmable gate array) based prototype for an F-16 PCA seriously impacted by the DMS problem.