On acceleration of logic circuits optimization using implication relations

Abstract

In logic synthesis the multi-level logic optimization methods using implication analysis has high performance but it needs a lot of computational time because of using test pattern generation to identify redundant faults. In this paper we proposed a fast redundancy identification method using implication relation instead of test pattern generation. Experimental results for benchmark circuits clearly show that the proposed method can accelerate the speed to identify redundancies without declining of the ability of the optimization.