Zynq FPGA Based System Design for Video Surveillance with Sobel Edge Detection

2018 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS) Pub Date : 2018-12-01 DOI:10.1109/ISES.2018.00025

S. Eetha, Sonali Agarwal, Srikanth Neelam

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引用次数: 13

Abstract

Advancements in semiconductor domain gave way to realize numerous applications in Video Surveillance using Computer vision and Deep learning, Video Surveillances in Industrial automation, Security, ADAS, Live traffic analysis etc. through image understanding improves efficiency. Image understanding requires input data with high precision which is dependent on Image resolution and location of camera. The data of interest can be thermal image or live feed coming for various sensors. Composite(CVBS) is a popular video interface capable of streaming upto HD(1920x1080) quality. Unlike high speed serial interfaces like HDMI/MIPI CSI, Analog composite video interface is a single wire standard supporting longer distances. Image understanding requires edge detection and classification for further processing. Sobel filter is one the most used edge detection filter which can be embedded into live stream. This paper proposes Zynq FPGA based system design for video surveillance with Sobel edge detection, where the input Composite video decoded (Analog CVBS input to YCbCr digital output), processed in HW and streamed to HDMI display simultaneously storing in SD memory for later processing. The HW design is scalable for resolutions from VGA to Full HD for 60fps and 4K for 24fps. The system is built on Xilinx ZC702 platform and TVP5146 to showcase the functional path.

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基于 Zynq FPGA 的索贝尔边缘检测视频监控系统设计

半导体领域的进步为利用计算机视觉和深度学习实现视频监控、工业自动化视频监控、安防、ADAS、实时交通分析等众多应用提供了途径，通过图像理解提高了效率。图像理解需要高精度的输入数据，这取决于图像分辨率和摄像头的位置。相关数据可以是热图像，也可以是各种传感器的实时图像。复合接口（CVBS）是一种常用的视频接口，能够传输高达高清（1920x1080）质量的数据流。与 HDMI/MIPI CSI 等高速串行接口不同，模拟复合视频接口是单线标准，支持更长距离。图像理解需要边缘检测和分类，以便进一步处理。Sobel 滤波器是最常用的边缘检测滤波器之一，可以嵌入到实时流中。本文提出了基于 Zynq FPGA 的视频监控系统设计，该系统具有 Sobel 边缘检测功能，可对输入的复合视频进行解码（模拟 CVBS 输入到 YCbCr 数字输出），在硬件中进行处理，然后流式传输到 HDMI 显示器，同时将其存储到 SD 存储器中，以供日后处理。硬件设计可扩展分辨率，从 VGA 到 60fps 的全高清和 24fps 的 4K。该系统基于 Xilinx ZC702 平台和 TVP5146 构建，以展示功能路径。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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2018 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS)

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