Analysis, Design and Modeling of Millimeter-Wave Wilkinson Power Combiner for 5G Phased Array

Abstract

A Wilkinson power combiner performed in shielded coplanar waveguide is presented in this paper. A lumped circuit model has been proposed for the design and optimization of this work. Fabricated in 65-nm CMOS technology, the Wilkinson power combiner occupies a core chip area of 266 × 382 μm2. The measured insertion loss is 0.92-1.33 dB at 20-40 GHz. The input return loss is better than 15.5 dB and the output return loss is better than 25 dB from 20 to 40 GHz. The port-to-port isolation is better than 14.5 dB from 20 to 40 GHz.