High-coverage analog IP block test generation methodology using low-cost signal generation and output response analysis

Abstract

Today, testing of AMS circuits needs to improve quality towards ppb test escape levels as well as decrease the test development time to reduce the IC lead time. A defect-oriented solution can improve quality by focusing on structural tests that can detect defects more efficiently than traditional functional tests, while test reuse can decrease test development time on ICs built with reusable IP blocks. A defect-oriented built-in self-test (BIST) approach integrates both solutions. This paper proposes a test development methodology for analog IP blocks based on such defect-oriented BIST framework. The methodology allows for achieving the target defect coverage at the lowest possible cost. Co-designing the IP with the DfT structures allows accounting for any non-idealities that the DfT may add to the IP. Test structures cost is limited by using low-cost signal generation and a new output response analyzer (ORA). The proposed methodology is demonstrated on two case studies. The results show that coverages higher than 90% are possible using a simple digital pulse signal and an ORA with only 4 bits of accuracy, while coverages higher than 95% are possible with 6 bits, offering a good trade-off between coverage and cost.