A 77.1-dB 6.25-MHz-BW Pipeline SAR ADC with Enhanced Interstage Gain Error Shaping and Quantization Error Shaping

Abstract

This paper presents an enhanced interstage gain error shaping technique that adopts a digital error feedback technique to extend the interstage gain error tolerance by 5 times. This paper also proposes a passive quantization error shaping technique that reduces the ratio of the two-input-pair comparator by 2.7 times. A prototype equipped with the proposed techniques is implemented in 40nm CMOS. It achieves a SNDR of 77.1 dB over 6.25-MHz bandwidth while operating at 100 MS/s and consuming 1.38 mW. It achieves 173.7 dB Schreier FoM.