{"title":"The Development of $K^{N}$ Voltage Gain Switched-Capacitor DC-DC Converter Based on Parallel Fibonacci-Type Converter","authors":"Ratanaubol Rubpongse, Wanglok Do, K. Eguchi","doi":"10.1109/ICEAST.2019.8802542","DOIUrl":null,"url":null,"abstract":"To provide high stepped-up voltages to energy harvesting systems, this paper proposes ‘$\\boldsymbol{K^{N}}(\\boldsymbol{K}=1,2,\\ldots)$ and ($\\boldsymbol{N}=1,2,\\ldots$) voltage gain switched-capacitor DC-DC converter’ based on parallel Fibonacci-Type converters. The suggested converter topology leads the proposed converter to generate K power of N voltage gain in every clock cycle. Moreover, the power efficiency of the proposed converter is higher than that of traditional converters when they are operated on high gain mode. Since the output capacitance of the suggested converter is smaller than that of the conventional converter, it is possible to reduce the occupation area when IC implementation of the proposed one is performed.","PeriodicalId":188498,"journal":{"name":"2019 5th International Conference on Engineering, Applied Sciences and Technology (ICEAST)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 5th International Conference on Engineering, Applied Sciences and Technology (ICEAST)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICEAST.2019.8802542","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
To provide high stepped-up voltages to energy harvesting systems, this paper proposes ‘$\boldsymbol{K^{N}}(\boldsymbol{K}=1,2,\ldots)$ and ($\boldsymbol{N}=1,2,\ldots$) voltage gain switched-capacitor DC-DC converter’ based on parallel Fibonacci-Type converters. The suggested converter topology leads the proposed converter to generate K power of N voltage gain in every clock cycle. Moreover, the power efficiency of the proposed converter is higher than that of traditional converters when they are operated on high gain mode. Since the output capacitance of the suggested converter is smaller than that of the conventional converter, it is possible to reduce the occupation area when IC implementation of the proposed one is performed.