Development of a pogo pin assembly and via design for multi-gigabit interfaces on automated test equipment

Abstract

I/O cells operating up to 10 Gb/s, are now becoming standard blocks in complex integrated circuits (ICs). Integration of these multiple I/O cells in conjunction with other cores (e.g. mixed-signal) and higher power requirements has increased the pin count for some devices to above one thousand pins. This presents tough challenges for the automated test equipment (ATE) industry, in terms of developing solutions to address the data rate and routing density. This paper demonstrates a novel approach for designing a high density Pogo pin transition to a multilayer planar PCB structure that achieves not only the required 10 Gb/s performance but also maintains the necessary density, and cost requirements that are inherent to an ATE solution.