Performance enhancement of junctionless nanowire FET with laterally graded channel doping and high-K spacers

Abstract

We propose the use of laterally graded channel doping and High-K Spacers positioned on both sides of gate oxide to improve the Performance and thereby, the scalability of Junctionless Nanowire Field Effect Transistors (JLNWFET). The performance parameters of the device considered in this study are ION/IOFF ratio, Drain-Induced Barrier Lowering (DIBL) and Sub Threshold Slope (SS). Using extensive 3-D TCAD simulations, we have analyzed that the OFF-state leakage, DIBL and SS can be reduced owing to the combined use of laterally graded-doping channel and High-k Spacers.