Edge Verification: Ensuring Correctness under Resource Constraints

Abstract

Verification is one of the central tasks in circuit and system design. Since the components are used in several safety critical applications, functional correctness has to be ensured. But due to the increasing complexity, complete verification can often not be guaranteed. As a result, modern verification approaches have to cope with limited resources available, like time or computational power of available machines. Analogously to edge computing, resources constraint computing has to be considered in the context of verification, called Edge Verification in the following. Concepts are presented that allow efficient verification. This might be either by self-verification, where the verification hardware is included in the fabricated device, or by polynomial verification, where the synthesis process is restricted to guarantee that the generated circuit can be verified in polynomial time. For the later one, a case study is given for efficient polynomial formal verification of totally symmetric functions with short delay.