Low area FSM-based memory BIST for synchronous SRAM

Abstract

As the memory enters submicron technology, new test algorithm that will be able to give a better fault coverage such as to detect all intra-word coupling fault (CF) has been widely developed. In order to implement this algorithm to the memory, test technique such as BIST is utilized. Common types of memory built-in-self test (MBIST); microcode-based MBIST and FSM-based MBIST. The popular approach of designing various kind of MBIST architectures are either by targeting to reach specific testing requirement such as on full speed and at speed or by considering the cost-constraint and area overhead such low-cost or low-area design. In this paper, FSM-based BIST is designed to be able detecting all intra-word coupling fault (CF) in a synchronous SRAM under low- area constraint of test requirement.