Efficient implementation of low bit rate 1.6 Kbps speech coder using field programmable gate arrays

Abstract

The cost-effective hardware architecture of a low bit rate 1.6 Kbit/s LPC (linear predictive coefficient)-based vocoder is proposed. The proposed architecture integrates both algorithms of the encoder and decoder. In the encoder, a simple finite state machine is presented to compute the autocorrelation function of speech. At the decoder side, efficient circuits are designed to transfer LSP (lne spectrum pair) to LPC. Only 29000 gate counts of XILINX XC4036XL FPGA are used to implement the vocoder.