Pub Date : 2001-09-26DOI: 10.1109/SIPS.2001.957354
N. Ling, N. Wang
We present an architecture for real-time digital HDTV video decoding. Our technique is based on a dual decoding datapath controlled in a fixed schedule with an efficient write-back scheme for anchor pictures. Unlike other decoding approaches such as the slice bar decoding method and the crossing-divided method, our scheme reduces the memory access contention problem to achieve real-time HDTV decoding without a high cost in overall decoder buffers, architecture, and bus. Our simulation shows that with a relatively low rate 81 MHz clock, our decoder can decode MPEG-2 MP@HL HDTV in real-time, based on an ATSC video format of 1920/spl times/1080 pixels/frame at 30 frames/s, at a bit rate of 18 to 20 Mbit/s.
{"title":"A real-time HDTV video decoder","authors":"N. Ling, N. Wang","doi":"10.1109/SIPS.2001.957354","DOIUrl":"https://doi.org/10.1109/SIPS.2001.957354","url":null,"abstract":"We present an architecture for real-time digital HDTV video decoding. Our technique is based on a dual decoding datapath controlled in a fixed schedule with an efficient write-back scheme for anchor pictures. Unlike other decoding approaches such as the slice bar decoding method and the crossing-divided method, our scheme reduces the memory access contention problem to achieve real-time HDTV decoding without a high cost in overall decoder buffers, architecture, and bus. Our simulation shows that with a relatively low rate 81 MHz clock, our decoder can decode MPEG-2 MP@HL HDTV in real-time, based on an ATSC video format of 1920/spl times/1080 pixels/frame at 30 frames/s, at a bit rate of 18 to 20 Mbit/s.","PeriodicalId":246898,"journal":{"name":"2001 IEEE Workshop on Signal Processing Systems. SiPS 2001. Design and Implementation (Cat. No.01TH8578)","volume":"11 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114376505","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-09-26DOI: 10.1109/SIPS.2001.957365
B. Dinechin, Christophe Monat, F. Rastello
This paper addresses the problem of improving the execution performance of saturated reduction loops on fixed-point instruction-level parallel digital signal processors (DSPs). We first introduce "bit-exact" transformations, that are suitable for use in the ETSI and the ITU speech coding applications. We then present "approximate" transformations, the relative precision of which we are able to compare. Our main results rely on the properties of the saturated arithmetic.
{"title":"Parallel execution of the saturated reductions","authors":"B. Dinechin, Christophe Monat, F. Rastello","doi":"10.1109/SIPS.2001.957365","DOIUrl":"https://doi.org/10.1109/SIPS.2001.957365","url":null,"abstract":"This paper addresses the problem of improving the execution performance of saturated reduction loops on fixed-point instruction-level parallel digital signal processors (DSPs). We first introduce \"bit-exact\" transformations, that are suitable for use in the ETSI and the ITU speech coding applications. We then present \"approximate\" transformations, the relative precision of which we are able to compare. Our main results rely on the properties of the saturated arithmetic.","PeriodicalId":246898,"journal":{"name":"2001 IEEE Workshop on Signal Processing Systems. SiPS 2001. Design and Implementation (Cat. No.01TH8578)","volume":"382 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129373378","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-09-26DOI: 10.1109/SIPS.2001.957360
R. J. Bril, C. Hentschel, Elisabeth F. M. Steffens, M. Gabrani, G. V. Loo, J. Gelissen
Over the past years, there has been a considerable amount of research in the field of QoS support for (distributed) multimedia systems, ie, multimedia processing in, for example, a (networked) workstation environment. QoS for multimedia systems is about media processing in software, using dynamically scalable functions, and trading resources for quality. Unlike QoS for mainstream multimedia systems, QoS support for high volume electronics (HVE) consumer terminals (CT), such as digital TV sets, digitally improved analog TV sets and STB (set-top boxes), has received little attention in the literature. This paper considers multimedia QoS for consumer terminals, with focus on the high-quality video domain.
{"title":"Multimedia QoS in consumer terminals","authors":"R. J. Bril, C. Hentschel, Elisabeth F. M. Steffens, M. Gabrani, G. V. Loo, J. Gelissen","doi":"10.1109/SIPS.2001.957360","DOIUrl":"https://doi.org/10.1109/SIPS.2001.957360","url":null,"abstract":"Over the past years, there has been a considerable amount of research in the field of QoS support for (distributed) multimedia systems, ie, multimedia processing in, for example, a (networked) workstation environment. QoS for multimedia systems is about media processing in software, using dynamically scalable functions, and trading resources for quality. Unlike QoS for mainstream multimedia systems, QoS support for high volume electronics (HVE) consumer terminals (CT), such as digital TV sets, digitally improved analog TV sets and STB (set-top boxes), has received little attention in the literature. This paper considers multimedia QoS for consumer terminals, with focus on the high-quality video domain.","PeriodicalId":246898,"journal":{"name":"2001 IEEE Workshop on Signal Processing Systems. SiPS 2001. Design and Implementation (Cat. No.01TH8578)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130755934","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-09-26DOI: 10.1109/SIPS.2001.957323
H. Meyr
Summary form only given. Advanced communication systems obey a generalized Moore's law. Not only does hardware complexity double every 18 months, but also the other performance indicators such as program size or memory content-increase by a factor of two in a period of one and a half and three years, to mention two examples. The drawing force behind this growth is the algorithmic complexity which is needed to design communication systems operating close to the information theoretic limits: near optimum system performance is bound to exponentially increasing algorithmic complexity. Stated differently, the usefulness for the user only grows logarithmically with complexity. Basically, this logarithmic complexity provides the rational for the continued growth of the semiconductor industry. Advanced communication systems will be implemented as reconfigurable, heterogeneous multiprocessor platforms. This hypothesis is based on the fundamental trade-off between computational efficiency (MOPS/mW) and flexibility. While programmable devices (processors or DSPs) have the highest degree of flexibility, they have at least a two to three orders of magnitude smaller computational efficiency than the intrinsic computational efficiency (ICE) of fixed architectures. Hence, since power is the limiting factor, the SOCs of the future will carefully match algorithm with architecture to achieve an optimum. ("just as much flexibility as needed"). These SOC's will, therefore, become application specific platforms.
{"title":"Why we need all these MIPS in future wireless communication systems-and how to design algorithms and architecture for these systems","authors":"H. Meyr","doi":"10.1109/SIPS.2001.957323","DOIUrl":"https://doi.org/10.1109/SIPS.2001.957323","url":null,"abstract":"Summary form only given. Advanced communication systems obey a generalized Moore's law. Not only does hardware complexity double every 18 months, but also the other performance indicators such as program size or memory content-increase by a factor of two in a period of one and a half and three years, to mention two examples. The drawing force behind this growth is the algorithmic complexity which is needed to design communication systems operating close to the information theoretic limits: near optimum system performance is bound to exponentially increasing algorithmic complexity. Stated differently, the usefulness for the user only grows logarithmically with complexity. Basically, this logarithmic complexity provides the rational for the continued growth of the semiconductor industry. Advanced communication systems will be implemented as reconfigurable, heterogeneous multiprocessor platforms. This hypothesis is based on the fundamental trade-off between computational efficiency (MOPS/mW) and flexibility. While programmable devices (processors or DSPs) have the highest degree of flexibility, they have at least a two to three orders of magnitude smaller computational efficiency than the intrinsic computational efficiency (ICE) of fixed architectures. Hence, since power is the limiting factor, the SOCs of the future will carefully match algorithm with architecture to achieve an optimum. (\"just as much flexibility as needed\"). These SOC's will, therefore, become application specific platforms.","PeriodicalId":246898,"journal":{"name":"2001 IEEE Workshop on Signal Processing Systems. SiPS 2001. Design and Implementation (Cat. No.01TH8578)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132919750","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-09-26DOI: 10.1109/SIPS.2001.957331
M. Arnold, T. Bailey, J. Cowles, C. Walter
The complex-logarithmic number system (CLNS), which represents each complex point in log/polar coordinates, may be practical to implement the fast Fourier transform (FFT). The roots of unity needed by the FFT have exact representations in CLNS and do not require a ROM. We present an error analysis and simulation results for a radix-two FFT that compares a rectangular fixed-point representation of complex numbers to the CLNS. We observe that the CLNS saves 9-12 bits in word-size for 256-1024 point FFTs compared to the fixed-point number system while producing comparable accuracy.
{"title":"Analysis of complex LNS FFTs","authors":"M. Arnold, T. Bailey, J. Cowles, C. Walter","doi":"10.1109/SIPS.2001.957331","DOIUrl":"https://doi.org/10.1109/SIPS.2001.957331","url":null,"abstract":"The complex-logarithmic number system (CLNS), which represents each complex point in log/polar coordinates, may be practical to implement the fast Fourier transform (FFT). The roots of unity needed by the FFT have exact representations in CLNS and do not require a ROM. We present an error analysis and simulation results for a radix-two FFT that compares a rectangular fixed-point representation of complex numbers to the CLNS. We observe that the CLNS saves 9-12 bits in word-size for 256-1024 point FFTs compared to the fixed-point number system while producing comparable accuracy.","PeriodicalId":246898,"journal":{"name":"2001 IEEE Workshop on Signal Processing Systems. SiPS 2001. Design and Implementation (Cat. No.01TH8578)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129790305","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-09-26DOI: 10.1109/SIPS.2001.957340
M. J. Absar, Sapna George
The theory and design of critically sampled perfect reconstruction (PR) uniform filter bank (FB) is well established. However, the principles of non-uniform PR FB are still an active research topic. A number of necessary (compatibility) conditions have been identified, which any set of integer decimation factors must satisfy for existence of a realizable maximally-decimated perfect-reconstruction non-uniform filter bank. The search for a compatible-set, in the neighborhood of a desired set of decimation factors, can be computationally prohibitive, as it is exponential to the number of filters in the bank. We propose a branch-and-bound algorithm to efficiently search for compatible-sets. We present experimental results for a compatible set of a 26-filter bank, matching the critical bands of the human auditory system very closely.
{"title":"On the search for compatible numbers in the design of maximally decimated perfect reconstruction non-uniform filter bank","authors":"M. J. Absar, Sapna George","doi":"10.1109/SIPS.2001.957340","DOIUrl":"https://doi.org/10.1109/SIPS.2001.957340","url":null,"abstract":"The theory and design of critically sampled perfect reconstruction (PR) uniform filter bank (FB) is well established. However, the principles of non-uniform PR FB are still an active research topic. A number of necessary (compatibility) conditions have been identified, which any set of integer decimation factors must satisfy for existence of a realizable maximally-decimated perfect-reconstruction non-uniform filter bank. The search for a compatible-set, in the neighborhood of a desired set of decimation factors, can be computationally prohibitive, as it is exponential to the number of filters in the bank. We propose a branch-and-bound algorithm to efficiently search for compatible-sets. We present experimental results for a compatible set of a 26-filter bank, matching the critical bands of the human auditory system very closely.","PeriodicalId":246898,"journal":{"name":"2001 IEEE Workshop on Signal Processing Systems. SiPS 2001. Design and Implementation (Cat. No.01TH8578)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130509795","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-09-26DOI: 10.1109/SIPS.2001.957362
Naresh R Shanbhag
Summary form only given. Next generation multimedia communications are characterized by increasing functionality, higher mobility and ubiquity of access. Advances in semiconductor technology has enabled the implementation of complex multimedia microsystems. However, this has also raised numerous challenges at the highest (system) and lowest (physical) levels of the design hierarchy for producing reliable and energy-efficient multimedia communication systems. Multimedia communication systems offer unique opportunities to address these problems due to the inherent redundancy in naturally occurring signals, the relaxed latency requirements, and the statistical nature of metrics, such as SNR, used commonly to quantify the functionality of such systems. Most importantly, in multimedia communication systems, algorithmic, architectural and circuit design issues are closely intertwined and better understood than in the case of general purpose computing. This raises the possibility of systematically optimizing energy and performance across the three domains. Two distinct design philosophies for implementing reliable and energy-efficient multimedia communication systems can be considered. The first approach, termed as noise-tolerance, is motivated from the communication and information-theoretic principle that energy-efficiency in the presence of noise is better achieved through error-control as opposed to noise control. The second approach relies on exploiting environmental dynamism, i.e., the inherent variability of environmental factors influencing the statistics of the multimedia signals being processed.
{"title":"Reliable low-power multimedia communication systems","authors":"Naresh R Shanbhag","doi":"10.1109/SIPS.2001.957362","DOIUrl":"https://doi.org/10.1109/SIPS.2001.957362","url":null,"abstract":"Summary form only given. Next generation multimedia communications are characterized by increasing functionality, higher mobility and ubiquity of access. Advances in semiconductor technology has enabled the implementation of complex multimedia microsystems. However, this has also raised numerous challenges at the highest (system) and lowest (physical) levels of the design hierarchy for producing reliable and energy-efficient multimedia communication systems. Multimedia communication systems offer unique opportunities to address these problems due to the inherent redundancy in naturally occurring signals, the relaxed latency requirements, and the statistical nature of metrics, such as SNR, used commonly to quantify the functionality of such systems. Most importantly, in multimedia communication systems, algorithmic, architectural and circuit design issues are closely intertwined and better understood than in the case of general purpose computing. This raises the possibility of systematically optimizing energy and performance across the three domains. Two distinct design philosophies for implementing reliable and energy-efficient multimedia communication systems can be considered. The first approach, termed as noise-tolerance, is motivated from the communication and information-theoretic principle that energy-efficiency in the presence of noise is better achieved through error-control as opposed to noise control. The second approach relies on exploiting environmental dynamism, i.e., the inherent variability of environmental factors influencing the statistics of the multimedia signals being processed.","PeriodicalId":246898,"journal":{"name":"2001 IEEE Workshop on Signal Processing Systems. SiPS 2001. Design and Implementation (Cat. No.01TH8578)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114939957","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-09-26DOI: 10.1109/SIPS.2001.957357
Y. Hwang, Shi-Shen Wang, Yun-Chiang Wang
An efficient algorithm and its VLSI architecture design for real-time shape adaptive zerotree coding (SA-ZTC) are presented. The proposed algorithm takes the DWT coefficients of the image as input and encodes the quantized coefficients efficiently to achieve the data compression. Most other wavelet coefficient-coding algorithms cannot provide real-time computation because they use multi-pass algorithms to decide the zerotrees formed by the wavelet coefficients. In contrast, the proposed SA-ZTC adopts a one pass algorithm and thus greatly reduces the computation time for real-time processing. Besides, the proposed architecture can be equally applied to both whole image coding without shape mask (eg, JPEG 2000) and object-based image coding with shape mask (eg, MPEG-4). Experimental results indicate the proposed algorithm can achieve better coding efficiency than the widely adopted EZW and the performance is close to the multi-pass SPHIT algorithm. The derived architecture design is shown to be hardware cost-effective and capable of delivering real-time processing.
{"title":"Efficient algorithm and architecture designs for MPEG-4 shape adaptive video object coding","authors":"Y. Hwang, Shi-Shen Wang, Yun-Chiang Wang","doi":"10.1109/SIPS.2001.957357","DOIUrl":"https://doi.org/10.1109/SIPS.2001.957357","url":null,"abstract":"An efficient algorithm and its VLSI architecture design for real-time shape adaptive zerotree coding (SA-ZTC) are presented. The proposed algorithm takes the DWT coefficients of the image as input and encodes the quantized coefficients efficiently to achieve the data compression. Most other wavelet coefficient-coding algorithms cannot provide real-time computation because they use multi-pass algorithms to decide the zerotrees formed by the wavelet coefficients. In contrast, the proposed SA-ZTC adopts a one pass algorithm and thus greatly reduces the computation time for real-time processing. Besides, the proposed architecture can be equally applied to both whole image coding without shape mask (eg, JPEG 2000) and object-based image coding with shape mask (eg, MPEG-4). Experimental results indicate the proposed algorithm can achieve better coding efficiency than the widely adopted EZW and the performance is close to the multi-pass SPHIT algorithm. The derived architecture design is shown to be hardware cost-effective and capable of delivering real-time processing.","PeriodicalId":246898,"journal":{"name":"2001 IEEE Workshop on Signal Processing Systems. SiPS 2001. Design and Implementation (Cat. No.01TH8578)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127883040","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-09-26DOI: 10.1109/SIPS.2001.957329
Sheng-Feng Wang, Huai-Yi Hsu, A. Wu
Reed-Solomon (RS) codes play an important role in providing error protection and data integrity. Among various RS decoding algorithms, the Peterson-Gorenstein-Zierler (PGZ) in general has the least computational complexity for small t values. However, unlike the iterative approaches (e.g., Berlekamp-Massey algorithm), it will encounter divide-by-zero problems in solving multiple t values. We propose a multi-mode hardware architecture for error number ranging from zero to three. We first propose a cost-down technique to reduce the hardware complexity of a t=3 decoder. Then, we perform an algorithmic-level derivation to identify the configurable feature of our design. With the manipulations, we are able to perform multi-mode RS decoding in one unified VLSI architecture with a very simple control scheme. The very low cost and simple datapath make our design a good choice in small-footprint embedded VLSI systems such as error control coding (ECC) in memory systems.
{"title":"A very low-cost multi-mode Reed-Solomon decoder based on Peterson-Gorenstein-Zierler algorithm","authors":"Sheng-Feng Wang, Huai-Yi Hsu, A. Wu","doi":"10.1109/SIPS.2001.957329","DOIUrl":"https://doi.org/10.1109/SIPS.2001.957329","url":null,"abstract":"Reed-Solomon (RS) codes play an important role in providing error protection and data integrity. Among various RS decoding algorithms, the Peterson-Gorenstein-Zierler (PGZ) in general has the least computational complexity for small t values. However, unlike the iterative approaches (e.g., Berlekamp-Massey algorithm), it will encounter divide-by-zero problems in solving multiple t values. We propose a multi-mode hardware architecture for error number ranging from zero to three. We first propose a cost-down technique to reduce the hardware complexity of a t=3 decoder. Then, we perform an algorithmic-level derivation to identify the configurable feature of our design. With the manipulations, we are able to perform multi-mode RS decoding in one unified VLSI architecture with a very simple control scheme. The very low cost and simple datapath make our design a good choice in small-footprint embedded VLSI systems such as error control coding (ECC) in memory systems.","PeriodicalId":246898,"journal":{"name":"2001 IEEE Workshop on Signal Processing Systems. SiPS 2001. Design and Implementation (Cat. No.01TH8578)","volume":"272 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125832028","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-09-26DOI: 10.1109/SIPS.2001.957322
H. Boelcskei
Summary form only given. The requirements on data rate and quality of service of future wireless communications systems call for new digital signal processing techniques to increase spectrum efficiency and improve link reliability. Deploying multiple antennas at both transmitter and receiver of a wireless link (MIMO technology) has the potential to achieve these ambitious goals. MIMO techniques are starting to find their way into standards, such as UMTS and IEEE 802.16. This article gives an overview of MIMO wireless covering issues such as propagation models, broadband transceivers, signaling techniques and coding and modulation. Special emphasis is put on the digital signal processing aspects.
{"title":"Digital signal processing challenges in MIMO wireless communications","authors":"H. Boelcskei","doi":"10.1109/SIPS.2001.957322","DOIUrl":"https://doi.org/10.1109/SIPS.2001.957322","url":null,"abstract":"Summary form only given. The requirements on data rate and quality of service of future wireless communications systems call for new digital signal processing techniques to increase spectrum efficiency and improve link reliability. Deploying multiple antennas at both transmitter and receiver of a wireless link (MIMO technology) has the potential to achieve these ambitious goals. MIMO techniques are starting to find their way into standards, such as UMTS and IEEE 802.16. This article gives an overview of MIMO wireless covering issues such as propagation models, broadband transceivers, signaling techniques and coding and modulation. Special emphasis is put on the digital signal processing aspects.","PeriodicalId":246898,"journal":{"name":"2001 IEEE Workshop on Signal Processing Systems. SiPS 2001. Design and Implementation (Cat. No.01TH8578)","volume":"258 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133436665","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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