A. Scuderi, D. Cristaudo, F. Carrara, G. Palmisano
{"title":"A high performance silicon bipolar monolithic RF linear power amplifier for W-LAN IEEE 802.11g applications","authors":"A. Scuderi, D. Cristaudo, F. Carrara, G. Palmisano","doi":"10.1109/RFIC.2004.1320532","DOIUrl":null,"url":null,"abstract":"A monolithic 2.5 GHz linear power amplifier for W-LAN IEEE 802.11g applications was integrated using a low cost 22 GHz f/sub T/ silicon bipolar process. The three-stage power amplifier exhibits a 26 dBm output 1 dB compression point, 30 dB power gain, and 52% maximum power-added efficiency, while using a low quiescent current, of 40 mA. Thanks to an optimized linearization technique, the power amplifier is able to comply with the stringent error vector magnitude requirement of the standard up to a 21.5 dBm output power level, with a 32% power-added efficiency. The power amplifier includes advanced bias functionalities and a fully integrated average channel power detector.","PeriodicalId":140604,"journal":{"name":"2004 IEE Radio Frequency Integrated Circuits (RFIC) Systems. Digest of Papers","volume":"3 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"9","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2004 IEE Radio Frequency Integrated Circuits (RFIC) Systems. Digest of Papers","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/RFIC.2004.1320532","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 9
Abstract
A monolithic 2.5 GHz linear power amplifier for W-LAN IEEE 802.11g applications was integrated using a low cost 22 GHz f/sub T/ silicon bipolar process. The three-stage power amplifier exhibits a 26 dBm output 1 dB compression point, 30 dB power gain, and 52% maximum power-added efficiency, while using a low quiescent current, of 40 mA. Thanks to an optimized linearization technique, the power amplifier is able to comply with the stringent error vector magnitude requirement of the standard up to a 21.5 dBm output power level, with a 32% power-added efficiency. The power amplifier includes advanced bias functionalities and a fully integrated average channel power detector.
京公网安备 11010802042870号
京ICP备2023020795号-1
分享
求助内容：
应助结果提醒方式：
扫码关注我们
