Pub Date : 2004-06-06DOI: 10.1109/RFIC.2004.1320699
X. Huo, K.J. Chen, H. Luong, P. Chan
A physical based lumped element model is developed for lossy silicon substrates, considering both electric loss and eddy current loss induced by the substrate. A simplified ladder structure is used to accurately model the skin effect of the high conductivity silicon substrate. Good agreement with a full wave solver is obtained for inductors on different resistivity silicon substrates.
{"title":"Accurate modeling of lossy silicon substrate for on-chip inductors and transformers design","authors":"X. Huo, K.J. Chen, H. Luong, P. Chan","doi":"10.1109/RFIC.2004.1320699","DOIUrl":"https://doi.org/10.1109/RFIC.2004.1320699","url":null,"abstract":"A physical based lumped element model is developed for lossy silicon substrates, considering both electric loss and eddy current loss induced by the substrate. A simplified ladder structure is used to accurately model the skin effect of the high conductivity silicon substrate. Good agreement with a full wave solver is obtained for inductors on different resistivity silicon substrates.","PeriodicalId":140604,"journal":{"name":"2004 IEE Radio Frequency Integrated Circuits (RFIC) Systems. Digest of Papers","volume":"139 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127463839","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-06-06DOI: 10.1109/RFIC.2004.1320576
Juo-Jung Hung, T. Hancock, Gabriel M. Rebeiz
A monolithic SiGe balanced frequency doubler has been designed and measured for Ku-band application. The circuit operates with a 2 V supply voltage and consumes only 28 mW of DC power when the doubler is biased close to class B operation, with an input power of 1.5 dBm. An output power of 5-6 dBm is obtained from 15.4-18 GHz and the fundamental suppression is better than 25 dB. It has a high power added efficiency (PAE) of 9.2% and occupies only 700/spl times/350 /spl mu/m/sup 2/ of chip area.
{"title":"A high-efficiency miniaturized SiGe Ku-band balanced frequency doubler","authors":"Juo-Jung Hung, T. Hancock, Gabriel M. Rebeiz","doi":"10.1109/RFIC.2004.1320576","DOIUrl":"https://doi.org/10.1109/RFIC.2004.1320576","url":null,"abstract":"A monolithic SiGe balanced frequency doubler has been designed and measured for Ku-band application. The circuit operates with a 2 V supply voltage and consumes only 28 mW of DC power when the doubler is biased close to class B operation, with an input power of 1.5 dBm. An output power of 5-6 dBm is obtained from 15.4-18 GHz and the fundamental suppression is better than 25 dB. It has a high power added efficiency (PAE) of 9.2% and occupies only 700/spl times/350 /spl mu/m/sup 2/ of chip area.","PeriodicalId":140604,"journal":{"name":"2004 IEE Radio Frequency Integrated Circuits (RFIC) Systems. Digest of Papers","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125122460","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-06-06DOI: 10.1109/RFIC.2004.1320702
Jr-Wei Lin, C.C. Chen, J.K. Huang, Y. Cheng
With a complete performance investigation of the on-chip micromachined inductor with mechanical disturbances using ANSYS and HFSS simulators, an optimum structural design of the micromachined spiral inductors with fully CMOS compatible post-processes for RFIC applications is proposed in this paper. Via the incorporation of a sandwich dielectric membrane (0.7 /spl mu/m SiO/sub 2// 0.7 /spl mu/m Si/sub 3/N/sub 4// 0.7 /spl mu/m TEOS) to enhance the structural rigidity, the inductor can have better signal stability. As compared, the new design of a 5nH micromachined inductor can have less than 45% inductance variation than the conventional one while both devices operate at 8GHz but with 10 m/sec/sup 2/ acceleration. Meanwhile, using a cross shape instead of blanket membrane can also effectively eliminate the inductance variation induced by the working temperature change (20/spl deg/C to 75/spl deg/C). It's our belief that the new micromachined inductors can have not only high Q performance but also better signal stability suitable for wide range RFIC applications.
{"title":"An optimum design of the micromachined RF inductor","authors":"Jr-Wei Lin, C.C. Chen, J.K. Huang, Y. Cheng","doi":"10.1109/RFIC.2004.1320702","DOIUrl":"https://doi.org/10.1109/RFIC.2004.1320702","url":null,"abstract":"With a complete performance investigation of the on-chip micromachined inductor with mechanical disturbances using ANSYS and HFSS simulators, an optimum structural design of the micromachined spiral inductors with fully CMOS compatible post-processes for RFIC applications is proposed in this paper. Via the incorporation of a sandwich dielectric membrane (0.7 /spl mu/m SiO/sub 2// 0.7 /spl mu/m Si/sub 3/N/sub 4// 0.7 /spl mu/m TEOS) to enhance the structural rigidity, the inductor can have better signal stability. As compared, the new design of a 5nH micromachined inductor can have less than 45% inductance variation than the conventional one while both devices operate at 8GHz but with 10 m/sec/sup 2/ acceleration. Meanwhile, using a cross shape instead of blanket membrane can also effectively eliminate the inductance variation induced by the working temperature change (20/spl deg/C to 75/spl deg/C). It's our belief that the new micromachined inductors can have not only high Q performance but also better signal stability suitable for wide range RFIC applications.","PeriodicalId":140604,"journal":{"name":"2004 IEE Radio Frequency Integrated Circuits (RFIC) Systems. Digest of Papers","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125925242","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-06-06DOI: 10.1109/RFIC.2004.1320691
T. Copani, S. Smerzi, G. Palmisano
High-speed prescalers are critical blocks when designing circuits for multi-GHz applications as well as for new optical-fiber networks. In this paper, an enhancement technique is shown for Si-bipolar E/sup 2/CL dividers. The proposed circuit allows high-speed operation despite a low supply voltage while it avoids using emitter followers which could lead to dangerous unwanted oscillations. A divide-by-8 prescaler was fabricated in a 46-GHz-f/sub T/ Si-bipolar technology to work within a 10-GHz output frequency PLL. Measurements show the circuit works reliably up to 12 GHz and can still operate at 11 GHz with a supply voltage as low as 2.7 V.
{"title":"A novel prescaler for silicon bipolar multi-Gigahertz applications","authors":"T. Copani, S. Smerzi, G. Palmisano","doi":"10.1109/RFIC.2004.1320691","DOIUrl":"https://doi.org/10.1109/RFIC.2004.1320691","url":null,"abstract":"High-speed prescalers are critical blocks when designing circuits for multi-GHz applications as well as for new optical-fiber networks. In this paper, an enhancement technique is shown for Si-bipolar E/sup 2/CL dividers. The proposed circuit allows high-speed operation despite a low supply voltage while it avoids using emitter followers which could lead to dangerous unwanted oscillations. A divide-by-8 prescaler was fabricated in a 46-GHz-f/sub T/ Si-bipolar technology to work within a 10-GHz output frequency PLL. Measurements show the circuit works reliably up to 12 GHz and can still operate at 11 GHz with a supply voltage as low as 2.7 V.","PeriodicalId":140604,"journal":{"name":"2004 IEE Radio Frequency Integrated Circuits (RFIC) Systems. Digest of Papers","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126774881","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The paper describes work done on a LC-VCO to linearize its frequency-voltage (Kvco) characteristic in order to extend its versatility. The technology used is a standard 0.13 /spl mu/m CMOS supplied by 1.2 V. The optimization is made on the varactor stage of the resonator and gives a nearly constant Kvco (140/spl plusmn/10 MHz/V from 2.36 GHz to 2.44 GHz), in spite of the MOS varactor non-linear characteristic, with still a good pushing (9 MHz/V) and constant phase noise (-126 dBc/Hz at 3 MHz offset).
{"title":"Distributed MOS varactor biasing for VCO gain equalization in 0.13 /spl mu/m CMOS technology","authors":"Julien Mira, Thierry Divel, Serge Ramet, Jean-Baptiste, Deval, STMicroelectronics","doi":"10.1109/RFIC.2004.1320548","DOIUrl":"https://doi.org/10.1109/RFIC.2004.1320548","url":null,"abstract":"The paper describes work done on a LC-VCO to linearize its frequency-voltage (Kvco) characteristic in order to extend its versatility. The technology used is a standard 0.13 /spl mu/m CMOS supplied by 1.2 V. The optimization is made on the varactor stage of the resonator and gives a nearly constant Kvco (140/spl plusmn/10 MHz/V from 2.36 GHz to 2.44 GHz), in spite of the MOS varactor non-linear characteristic, with still a good pushing (9 MHz/V) and constant phase noise (-126 dBc/Hz at 3 MHz offset).","PeriodicalId":140604,"journal":{"name":"2004 IEE Radio Frequency Integrated Circuits (RFIC) Systems. Digest of Papers","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114311341","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-06-06DOI: 10.1109/RFIC.2004.1320624
K. Choi, D. Allstot, V. Krishnamurthy
A three-stage 900 MHz GSM power amplifier implemented in 2 mm/sup 2/ in 250 nm CMOS outputs 2 W and 1-5 W with 30 and 43% drain and power-added efficiencies with 3.0 and 2.5 V power supply voltages, respectively. A cross-coupled self-biased cascode configuration reduces maximum voltage stress in the class-E driver stage to 1.6 V/sub DD/ without the use of additional bias voltages. A programmable conduction angle technique is also introduced and demonstrated.
{"title":"A 900 MHz GSM PA in 250 nm CMOS with breakdown voltage protection and programmable conduction angle","authors":"K. Choi, D. Allstot, V. Krishnamurthy","doi":"10.1109/RFIC.2004.1320624","DOIUrl":"https://doi.org/10.1109/RFIC.2004.1320624","url":null,"abstract":"A three-stage 900 MHz GSM power amplifier implemented in 2 mm/sup 2/ in 250 nm CMOS outputs 2 W and 1-5 W with 30 and 43% drain and power-added efficiencies with 3.0 and 2.5 V power supply voltages, respectively. A cross-coupled self-biased cascode configuration reduces maximum voltage stress in the class-E driver stage to 1.6 V/sub DD/ without the use of additional bias voltages. A programmable conduction angle technique is also introduced and demonstrated.","PeriodicalId":140604,"journal":{"name":"2004 IEE Radio Frequency Integrated Circuits (RFIC) Systems. Digest of Papers","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116333668","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-06-06DOI: 10.1109/RFIC.2004.1320673
F. Gruson, G. Gaborit, P. Abele, H. Schumacher
We report on the realization of an image-reject receiver that covers the various WLAN bands in Europe, Japan and the US, fabricated using a low-cost, 0.8 /spl mu/m production-line SiGe-HBT process. A modified Gilbert mixer with a common-base input stage allows for a broadband RF operation from 2.5-6 GHz at a low supply voltage of 3 V. Broadband quadrature generation was achieved by using a fully integrated X-band VCO at 10 GHz in conjunction with a master-slave divider rather than using a polyphase filter or a quadrature VCO. While consuming less chip-area than competing solutions, we achieve an excellent image suppression of 40-45 dB without any post-tuning.
{"title":"A broadband SiGe mixer for 5-GHz WLAN applications with X-band quadrature generation and high image-rejection","authors":"F. Gruson, G. Gaborit, P. Abele, H. Schumacher","doi":"10.1109/RFIC.2004.1320673","DOIUrl":"https://doi.org/10.1109/RFIC.2004.1320673","url":null,"abstract":"We report on the realization of an image-reject receiver that covers the various WLAN bands in Europe, Japan and the US, fabricated using a low-cost, 0.8 /spl mu/m production-line SiGe-HBT process. A modified Gilbert mixer with a common-base input stage allows for a broadband RF operation from 2.5-6 GHz at a low supply voltage of 3 V. Broadband quadrature generation was achieved by using a fully integrated X-band VCO at 10 GHz in conjunction with a master-slave divider rather than using a polyphase filter or a quadrature VCO. While consuming less chip-area than competing solutions, we achieve an excellent image suppression of 40-45 dB without any post-tuning.","PeriodicalId":140604,"journal":{"name":"2004 IEE Radio Frequency Integrated Circuits (RFIC) Systems. Digest of Papers","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124102104","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-06-06DOI: 10.1109/RFIC.2004.1320658
Y. A. Eken, J. Uyemura
This work presents a comparison of the ring and LC VCOs to be used in multiple-GHz communication systems. Multiple-GHz CMOS ring and LC VCOs are implemented on the same chip and tested under similar conditions for a fair comparison. The prototype chip was fabricated using a 0.18 /spl mu/m CMOS process and includes three-stage ring and symmetrical LC VCOs aimed for this comparison. The ring VCO dissipates 50 mW at an oscillation frequency of 6.1 GHz, and exhibits -97.5 dBc/Hz phase noise (@ 1 MHz). The LC VCO has a maximum frequency of 3 GHz with a 46% tuning range and has -111.4dBc/Hz phase noise (@1 MHz) while using 3.6 mW.
{"title":"Multiple-GHz ring and LC VCOs in 0.18 /spl mu/m CMOS","authors":"Y. A. Eken, J. Uyemura","doi":"10.1109/RFIC.2004.1320658","DOIUrl":"https://doi.org/10.1109/RFIC.2004.1320658","url":null,"abstract":"This work presents a comparison of the ring and LC VCOs to be used in multiple-GHz communication systems. Multiple-GHz CMOS ring and LC VCOs are implemented on the same chip and tested under similar conditions for a fair comparison. The prototype chip was fabricated using a 0.18 /spl mu/m CMOS process and includes three-stage ring and symmetrical LC VCOs aimed for this comparison. The ring VCO dissipates 50 mW at an oscillation frequency of 6.1 GHz, and exhibits -97.5 dBc/Hz phase noise (@ 1 MHz). The LC VCO has a maximum frequency of 3 GHz with a 46% tuning range and has -111.4dBc/Hz phase noise (@1 MHz) while using 3.6 mW.","PeriodicalId":140604,"journal":{"name":"2004 IEE Radio Frequency Integrated Circuits (RFIC) Systems. Digest of Papers","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127592059","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-06-06DOI: 10.1109/RFIC.2004.1320570
M. A. Masud, H. Zirath, M. Ferndahl, H. Vickes
Small signal amplifiers at 20 and 40 GHz, based on a 90 nm CMOS process are demonstrated. A gain of 5.8 dB at 20 GHz for single stage has been obtained with a 1 dB compression point at 1 dBm. The corresponding figures for the 40 GHz amplifiers are 6 dB and -5.75 dBm. Noise figure for the 20 GHz amplifier is 6.4 dB. Both single gate access and double gate access transistors have been used in the design. DC power consumption of the 20 GHz single stage amplifier was found to be 10 mW whereas for the 40 GHz double stage amplifier it is approximately 19 mW. Total circuit area is 0.7/spl times/0.8 mm/sup 2/ for the single stage and 1/spl times/0.7 mm/sup 2/ for the 40 GHz double stage amplifier.
{"title":"90 nm CMOS MMIC amplifier","authors":"M. A. Masud, H. Zirath, M. Ferndahl, H. Vickes","doi":"10.1109/RFIC.2004.1320570","DOIUrl":"https://doi.org/10.1109/RFIC.2004.1320570","url":null,"abstract":"Small signal amplifiers at 20 and 40 GHz, based on a 90 nm CMOS process are demonstrated. A gain of 5.8 dB at 20 GHz for single stage has been obtained with a 1 dB compression point at 1 dBm. The corresponding figures for the 40 GHz amplifiers are 6 dB and -5.75 dBm. Noise figure for the 20 GHz amplifier is 6.4 dB. Both single gate access and double gate access transistors have been used in the design. DC power consumption of the 20 GHz single stage amplifier was found to be 10 mW whereas for the 40 GHz double stage amplifier it is approximately 19 mW. Total circuit area is 0.7/spl times/0.8 mm/sup 2/ for the single stage and 1/spl times/0.7 mm/sup 2/ for the 40 GHz double stage amplifier.","PeriodicalId":140604,"journal":{"name":"2004 IEE Radio Frequency Integrated Circuits (RFIC) Systems. Digest of Papers","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126352298","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-06-06DOI: 10.1109/RFIC.2004.1320679
Yang Xu, C. Boone, L. Pileggi
This paper describes metal-mask configurable RF circuits that offer reduced design and manufacturing risk, hence lowering nonrecurring engineering (NRE) costs. The base circuit fabric is configured for various wireless applications using only top metal and via layers. A two-stage design optimization methodology is used to optimally trade-off area and performance for design risk and cost. Measurement results are shown for a metal-mask configurable RF front-end circuit fabric that is configured for applications in 1.5 GHz GPS, 2.1 GHz WCDMA and 5 GHz WLAN using a 0.25 /spl mu/m 47 GHz f/sub T/ SiGe BiCMOS process. The final three metal and via layers are the application-specific physical design differences for the three front-end circuits. The three frontend designs consume 10.5 mA, 9.5 mA, and 8.5 mA from 2.5 V, provide noise figures of 2.5 dB, 2.8 dB and 4.5 dB, have conversion gains of 24.6 dB, 24.2 dB and 12 dB, and offer IIP3s of -8dBm, -9dBm and 4dBm, respectively.
{"title":"Metal-mask configurable RF front-end circuits","authors":"Yang Xu, C. Boone, L. Pileggi","doi":"10.1109/RFIC.2004.1320679","DOIUrl":"https://doi.org/10.1109/RFIC.2004.1320679","url":null,"abstract":"This paper describes metal-mask configurable RF circuits that offer reduced design and manufacturing risk, hence lowering nonrecurring engineering (NRE) costs. The base circuit fabric is configured for various wireless applications using only top metal and via layers. A two-stage design optimization methodology is used to optimally trade-off area and performance for design risk and cost. Measurement results are shown for a metal-mask configurable RF front-end circuit fabric that is configured for applications in 1.5 GHz GPS, 2.1 GHz WCDMA and 5 GHz WLAN using a 0.25 /spl mu/m 47 GHz f/sub T/ SiGe BiCMOS process. The final three metal and via layers are the application-specific physical design differences for the three front-end circuits. The three frontend designs consume 10.5 mA, 9.5 mA, and 8.5 mA from 2.5 V, provide noise figures of 2.5 dB, 2.8 dB and 4.5 dB, have conversion gains of 24.6 dB, 24.2 dB and 12 dB, and offer IIP3s of -8dBm, -9dBm and 4dBm, respectively.","PeriodicalId":140604,"journal":{"name":"2004 IEE Radio Frequency Integrated Circuits (RFIC) Systems. Digest of Papers","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128003391","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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