LCAM: Low-Cost Approximate Multiplier Design on FPGA

Abstract

Approximate multiplier is a computing unit, which reduces resource and power by sacrificing computational accuracy, and is widely used in fields such as image processing and deep neural networks. In this paper, a low-cost $\mathbf{8}\times \mathbf{8}$ unsigned approximate multiplier is proposed by considering FPGA architectural features. A stage-aware most significant bits (MSBs) selection scheme is designed for error recovery to trade off accuracy and resource usage. The proposed multiplier saves up to 19.7% LUT utilization while the accuracy only decreases 4%, compared to the accurate Xilinx multiplier IP.