Failure mechanisms of boards in a thin wafer level chip scale package

Abstract

Various studies have been conducted to study the effect of varying board thickness on thermo-mechanical reliability of BGA packages. Wafer level chip scale packages (WLCSP) have also been studied in this regard to determine the effect of PCB build-up thickness on the solder joint reliability [1]. The studies clearly demonstrate that the thinner Printed Circuit Boards (PCBs) result in longer thermo-mechanical fatigue life of solder joints for BGA. With the literature and past trends supporting the idea of thinner boards, manufacturer opted to move forward by decreasing the thickness of their PCBs to improve the reliability of their packages. The thickness was reduced from 1mm to 0.7mm by decreasing the thicknesses of individual layers and keeping the total number of layers constant. When subjected to thermal cycling, it was observed that 0.7mm board was failing earlier than the 1mm board. Since this behavior of a WLCSP contrasts with the past trends, it required extensive study to determine and understand the pre-mature physics of failure/causality of failure in 0.7mm board. In this paper, an effort is made to understand the mechanism which is causing an early failure in the thinner board. The effect of number & thicknesses of core layers, prepregs and Cu layers in the board has been studied through material characterization of both 1mm and 0.7mm boards. Further, a design optimization account has also been presented to improve the thermo-mechanical reliability of this package.