Modelling of 0.15μm Dual Gate PM-HEMTs by using Experimental Extraction

Abstract

In this paper are presented some new experimental results concerning 0.15μm dual gate PM-HEMTs obtained by using a new method of characterization. It consists of a step-by-step procedure which allows to extract the entire equivalent scheme of dual gate devices. All parasitic elements are determined by biasing the Dual Gate FET (DGFET) under 'cold' regime (Vds=0V) : the forward gates bias conditions allow to deduce the value of serie elements like access resistances and inductances from Zij parameters, and, the reverse gates bias conditions lead to the parallel pad and coupling capacitances from Yij parameters. For intrinsic elements, the cascode configuration has been retained : the DGFET is considered as being the association of two equivalent single gate transistors. On wafer three-ports S-parameters measurements are performed from 1.5 to 26.5 GHz with a specific test bench that we have developped in our laboratory.