Zhiwei Zong, Xin-yan Tang, Johan Nguyen, K. Khalaf, G. Mangraviti, Yao-Hong Liu, P. Wambacq
{"title":"A 28GHz Two-Way Current Combining Stacked-FET Power Amplifier in 22nm FD-SOI","authors":"Zhiwei Zong, Xin-yan Tang, Johan Nguyen, K. Khalaf, G. Mangraviti, Yao-Hong Liu, P. Wambacq","doi":"10.1109/CICC48029.2020.9075906","DOIUrl":null,"url":null,"abstract":"We present a two-way current combining power amplifier (PA) for 28GHz wireless communication. To boost the saturated output power (PSAT) and maintain a high power-added efficiency (PAE), a differential 3-stacked transistors structure is used for the unit PA cell. The stability factor and the PAE are improved with capacitive neutralization and shunt inductor intermediate node matching. Reliability issues under a 2.4V supply voltage are relieved with properly designed biasing and gate capacitances. The PA is implemented in a 22nm FD-SOI technology with a chip core area of 0.21 mm2, Measurement results show that the PA achieves a power gain of 27dB and a PSAT of 21.7dBm with a maximum PAE of 27.1% at 28GHz. The output 1dB compression point (P1aB) is 19.1 dBm. Measured PAE at P1dB and 6dB power back-off are 23% and 10.3%, respectively.","PeriodicalId":409525,"journal":{"name":"2020 IEEE Custom Integrated Circuits Conference (CICC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2020 IEEE Custom Integrated Circuits Conference (CICC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CICC48029.2020.9075906","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
We present a two-way current combining power amplifier (PA) for 28GHz wireless communication. To boost the saturated output power (PSAT) and maintain a high power-added efficiency (PAE), a differential 3-stacked transistors structure is used for the unit PA cell. The stability factor and the PAE are improved with capacitive neutralization and shunt inductor intermediate node matching. Reliability issues under a 2.4V supply voltage are relieved with properly designed biasing and gate capacitances. The PA is implemented in a 22nm FD-SOI technology with a chip core area of 0.21 mm2, Measurement results show that the PA achieves a power gain of 27dB and a PSAT of 21.7dBm with a maximum PAE of 27.1% at 28GHz. The output 1dB compression point (P1aB) is 19.1 dBm. Measured PAE at P1dB and 6dB power back-off are 23% and 10.3%, respectively.