A 6-bit 1.6-GS/s domino-SAR ADC in 55nm CMOS

Abstract

This paper presents a 6-bit 1.6-GS/s SAR ADC incorporating a domino-comparator architecture. The proposed domino-SAR architecture effectively speed up ADC operation. To further fasten the operating speed, a ping-pong operation is applied to achieve 1.6-GS/s. To against PVT variations, an adaptive sampler is proposed to adjust the allocated conversion time automatically. The ADC was implemented in 55nm LP CMOS. It consumes 5 mW from a 1.2-V supply. At Nyquist-rate, the simulated SNDR and SFDR are 35.4 and 52 dB respectively. Its ENOB is 5.6 bits, equivalent to a FOM of 64 fJ/conv.-step.