{"title":"Power Efficient UART Desing Using Capactive Load on Different Nanometer Technology FPGA","authors":"K. Kumar, D. Hussain, B. Pandey","doi":"10.21058/GJET.2019.52001","DOIUrl":null,"url":null,"abstract":"","PeriodicalId":170238,"journal":{"name":"Gyancity Journal of Engineering and Technology","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-07-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Gyancity Journal of Engineering and Technology","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.21058/GJET.2019.52001","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
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