Logic synthesis

Abstract

An average engineer working on an ASIC project designs between 200 ad 500 gates per week. With design complexity increasing and time-to-market becoming more critical, considerable attention is being focussed on how to improve productivity. Synthesis offers a great deal of promise. In this paper LSI Logic explain their approach to logic synthesis, both in terms of their inhouse tools and the ability to support third party routes. The Logic Expression Synthesizer (LES) and Logic Block Synthesizer (LBS) tools are discussed in detail. LBS can synthesize a variety of modules, for example carry-select adders, gray code counters and fall-through FIFOs: while LES is capable of outputting an optimised netlist from both low and high level forms of input, including FSM and RTL formats. Finally, future approaches to synthesis are discussed, including behavioural synthesis from VHDL.<>