J. Hezavei, N. Vijaykrishnan, M. J. Irwin, M. Kandemir, D. Duarte
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引用次数: 4
Abstract
An input sensitive table based power estimation technique is proposed. The proposed technique has been applied to different circuits and validated using circuit-level simulation for 0.25 /spl mu/m, 2.5 V CMOS technology. It is observed that the proposed scheme achieves an average error margin of 3.2% as compared to HSPICE, while running 27 times faster.
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