{"title":"An Experimental Cascade Cell Dynamic Memory","authors":"D. Stark, H. Watanabe, T. Furuyama","doi":"10.1109/VLSIC.1994.586230","DOIUrl":null,"url":null,"abstract":"Series connected storage cells provide greater storage density for a given DRAM technology. We introduce several new features to exploit this advantage: an extra wordline to allow read and restore of the serial bits in the same order, a shift register row decoder with variable size redundancy, and a sense amp exchange configuration to ameliorate inter-bitline noise, We have designed and fabricated an experimental 32M DRAM that shows these ideas are feasible.","PeriodicalId":350730,"journal":{"name":"Proceedings of 1994 IEEE Symposium on VLSI Circuits","volume":"6 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1994-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of 1994 IEEE Symposium on VLSI Circuits","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.1994.586230","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
Series connected storage cells provide greater storage density for a given DRAM technology. We introduce several new features to exploit this advantage: an extra wordline to allow read and restore of the serial bits in the same order, a shift register row decoder with variable size redundancy, and a sense amp exchange configuration to ameliorate inter-bitline noise, We have designed and fabricated an experimental 32M DRAM that shows these ideas are feasible.
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