Forward error correction for high-speed I/O

Abstract

Modern state-of-the-art high-speed (Gb/s) I/O links today rely exclusively upon an equalization-based transceiver to achieve a bit error-rate (BER) of 10-15. This paper explores the potential of applying forward error-correction (FEC) in such links to reduce power and BER. The FEC coding gain can be employed to lower the power consumed in the analog components (e.g., transmit driver, clock recovery unit (CRU)) since these do not scale with process technology. A BER improvement of six orders-of-magnitude and ten orders-of-magnitude is demonstrated for a 20" FR4 channel operating at 10 Gb/s with a LE and a DFE, respectively, using a BCH code. Savings in the encoder-decoder power overhead of up to 50% is demonstrated for a (63, 36, 11) BCH code using a novel gated decoder architecture.