Delay Optimization of 4-Bit ALU Designed in FS-GDI Technique

Abstract

Arithmetic Logic Unit (ALU) is an essential building block in many applications such as microprocessors, DSP, and image processing, while power efficiency is a general concern in VLSI design. This paper presents Delay time optimization of 4-bit ALU designed using full-swing gate diffusion input (GDI) technique. Simulations carried out in Cadence virtuoso using 65nm TSMC processes with a supply voltage of 1.2 volts and a frequency of 125 MHz, Simulation results revealed improvement in Delay time and overall Energy of the optimized ALU design.