Evaluating the Optimal Self-Checking Carry Propagate Adder for Cryptographic Processor

Abstract

With the increasing number of invasive attacks, cryptographic processors are becoming more susceptible to failure. Therefore, the desire for reliable hardware is becoming increasingly important. Since an adder is a vital component in the hardware design of cryptographic protocols, a reliable adder can significantly improve the vulnerability against invasive attacks. Adders with different architectures have already been widely studied and analyzed and appropriate types have been proposed based on the application. This paper considers the design of adder most suitable for reliable cryptographic operation and investigates the optimal self-checking carry propagate adder design offering the best possible performance in terms of latency, delay, and area. In terms of area versus delay, the self-checking parallel ripple carry adder (PRCA) with 23.4% area overhead as compared to the self-checking ripple carry adder (RCA) provides a delay efficiency of 70.31%. However, the area-delay product for 64-bit self-checking designs showed that the hybrid adder is 71.2%, 21.4%, and 37.9% more efficient than the RCA, PRCA and carry look-ahead adder design, respectively.